Searched refs:RegOpnd (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 531 auto RegOpnd = MI.getOperand(OpIdx).getReg(); in encodeMatrixIndexGPR32() local
532 assert(RegOpnd >= AArch64::W12 && RegOpnd <= AArch64::W15 && in encodeMatrixIndexGPR32()
534 return RegOpnd - AArch64::W12; in encodeMatrixIndexGPR32()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 808 SDNode *RegOpnd; in trySelect() local
816 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); in trySelect()
818 RegOpnd = in trySelect()
827 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in trySelect()
828 SDValue(RegOpnd, 0), ImmOpnd); in trySelect()
831 ReplaceNode(Node, RegOpnd); in trySelect()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 7644 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpAdd() local
7645 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpAdd()
7646 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpAdd()
7657 getTargetStreamer().emitDirectiveCpAdd(RegOpnd.getGPR32Reg()); in parseDirectiveCpAdd()
7677 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpLoad() local
7678 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpLoad()
7679 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpLoad()
7706 MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); in parseDirectiveCpLocal() local
7707 if (!RegOpnd.isGPRAsmReg()) { in parseDirectiveCpLocal()
7708 reportParseError(RegOpnd.getStartLoc(), "invalid register"); in parseDirectiveCpLocal()
[all …]
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| /llvm-project-15.0.7/bolt/lib/Target/X86/ |
| H A D | X86MCPlusBuilder.cpp | 1148 MCOperand RegOpnd = Inst.getOperand(0); in isStackAccess() local
1149 assert(RegOpnd.isReg() && "unexpected destination operand"); in isStackAccess()
1150 Reg = RegOpnd.getReg(); in isStackAccess()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 7974 TargetInstrInfo::RegSubRegPair getRegOrUndef(const MachineOperand &RegOpnd) { in getRegOrUndef() argument
7975 assert(RegOpnd.isReg()); in getRegOrUndef()
7976 return RegOpnd.isUndef() ? TargetInstrInfo::RegSubRegPair() : in getRegOrUndef()
7977 getRegSubRegPair(RegOpnd); in getRegOrUndef()
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