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Searched refs:RegC (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
528 Register RegC, in isProfitableToCommute() argument
552 if (!isPlainlyKilled(MI, RegC, LIS)) in isProfitableToCommute()
568 MCRegister FromRegC = getMappedReg(RegC, SrcRegMap); in isProfitableToCommute()
589 if (!noUseAfterLastDef(RegC, Dist, LastDefC)) in isProfitableToCommute()
613 if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge)) in isProfitableToCommute()
636 Register RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction() local
651 MCRegister FromRegC = getMappedReg(RegC, SrcRegMap); in commuteInstruction()
H A DTargetInstrInfo.cpp846 Register RegC = OpC.getReg(); in reassociateOps() local
856 if (Register::isVirtualRegister(RegC)) in reassociateOps()
857 MRI.constrainRegClass(RegC, RC); in reassociateOps()
877 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC) in reassociateOps()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp803 Register RegC = OpC.getReg(); in reassociateFMA() local
804 const TargetRegisterClass *RC = MRI.getRegClass(RegC); in reassociateFMA()
805 MRI.constrainRegClass(RegC, RC); in reassociateFMA()
943 get(FMAOpIdxInfo[Idx][InfoArrayIdxFAddInst]), RegC) in reassociateFMA()
985 get(FMAOpIdxInfo[Idx][InfoArrayIdxFAddInst]), RegC) in reassociateFMA()
1023 NewCRegPressure = BuildMI(*MF, Root.getDebugLoc(), get(FmaOp), RegC) in reassociateFMA()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5699 Register RegC = AddMI->getOperand(IdxOtherOpd).getReg(); in genSubAdd2SubSub() local
5719 .addReg(RegC, getKillRegState(RegCIsKill)); in genSubAdd2SubSub()