Searched refs:Reg128 (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 547 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
565 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
599 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
605 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
611 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
617 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
623 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
629 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
635 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
641 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 81 Register Reg128 = LowRegOp.getReg(); in splitMove() local
93 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl); in splitMove()
94 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed)); in splitMove()
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