Home
last modified time | relevance | path

Searched refs:ReadyCycle (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DVLIWMachineScheduler.cpp373 SUnit *SU, unsigned ReadyCycle) { in releaseNode() argument
374 if (ReadyCycle < MinReadyCycle) in releaseNode()
375 MinReadyCycle = ReadyCycle; in releaseNode()
379 if (ReadyCycle > CurrCycle || checkHazard(SU)) in releaseNode()
452 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle; in releasePending() local
454 if (ReadyCycle < MinReadyCycle) in releasePending()
455 MinReadyCycle = ReadyCycle; in releasePending()
457 if (ReadyCycle > CurrCycle) in releasePending()
H A DMachineScheduler.cpp2078 if (ReadyCycle > CurrCycle) in getLatencyStallCycles()
2079 return ReadyCycle - CurrCycle; in getLatencyStallCycles()
2266 if (ReadyCycle > CurrCycle) in releaseNode()
2270 if (ReadyCycle < MinReadyCycle) in releaseNode()
2271 MinReadyCycle = ReadyCycle; in releaseNode()
2406 if (ReadyCycle > NextCycle) { in bumpNode()
2407 NextCycle = ReadyCycle; in bumpNode()
2417 NextCycle = ReadyCycle; in bumpNode()
2533 if (ReadyCycle < MinReadyCycle) in releasePending()
2534 MinReadyCycle = ReadyCycle; in releasePending()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DVLIWMachineScheduler.h187 void releaseNode(SUnit *SU, unsigned ReadyCycle);
H A DMachineScheduler.h784 void releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue,
792 unsigned Cycles, unsigned ReadyCycle);
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp612 unsigned ReadyCycle = PendingQueue[i]->getHeight(); in ReleasePending() local
613 if (ReadyCycle < MinAvailableCycle) in ReleasePending()
614 MinAvailableCycle = ReadyCycle; in ReleasePending()
662 unsigned ReadyCycle = SU->getHeight(); in AdvancePastStalls() local
668 AdvanceToCycle(ReadyCycle); in AdvancePastStalls()