| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | LiveInterval.cpp | 1189 if (ReadI != E && ReadI->end <= Seg.start) { in add() 1191 if (ReadI != WriteI) in add() 1194 if (ReadI == WriteI) in add() 1197 while (ReadI != E && ReadI->end <= Seg.start) in add() 1198 *WriteI++ = *ReadI++; in add() 1201 assert(ReadI == E || ReadI->end > Seg.start); in add() 1204 if (ReadI != E && ReadI->start <= Seg.start) { in add() 1211 ++ReadI; in add() 1215 while (ReadI != E && coalescable(Seg, *ReadI)) { in add() 1217 ++ReadI; in add() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedKryoDetails.td | 344 def : InstRW<[KryoWrite_1cyc_XY_63ln, ReadI, ReadI], 356 def : InstRW<[KryoWrite_1cyc_XY_62ln, ReadI], 362 def : InstRW<[KryoWrite_2cyc_XY_XY_64ln, ReadI, ReadI], 482 def : InstRW<[KryoWrite_0cyc_XY_16ln, ReadI], 488 def : InstRW<[KryoWrite_0cyc_XY_16_1ln, ReadI, ReadI], 494 def : InstRW<[KryoWrite_2cyc_XY_3ln, ReadI], 542 def : InstRW<[KryoWrite_1cyc_XY_20ln, ReadI, ReadI], 548 def : InstRW<[KryoWrite_1cyc_X_17ln, ReadI, ReadI], 554 def : InstRW<[KryoWrite_1cyc_XY_18ln, ReadI, ReadI], 1781 def : InstRW<[KryoWrite_1cyc_XY_2ln, ReadI, ReadI], [all …]
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| H A D | AArch64Schedule.td | 27 def ReadI : SchedRead; // ALU
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| H A D | AArch64SchedFalkor.td | 107 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedKryo.td | 113 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64InstrFormats.td | 2016 Sched<[WriteI, ReadI]> { 2052 Sched<[WriteI, ReadI]> { 2080 Sched<[WriteI, ReadI, ReadI]> { 2104 Sched<[WriteI, ReadI, ReadI]> { 2133 Sched<[WriteI, ReadI, ReadI]> { 2422 Sched<[WriteI, ReadI]> { 2479 Sched<[WriteI, ReadI, ReadI]>; 2991 Sched<[WriteI, ReadI, ReadI]>; 3078 Sched<[WriteI, ReadI, ReadI]> { 3123 Sched<[WriteI, ReadI, ReadI]> { [all …]
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| H A D | AArch64SchedThunderX.td | 205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
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| H A D | AArch64SchedA53.td | 162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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| H A D | AArch64SchedA55.td | 219 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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| H A D | AArch64SchedCyclone.td | 868 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedTSV110.td | 110 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedExynosM3.td | 272 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedAmpere1.td | 675 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedA57.td | 114 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedExynosM4.td | 576 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedExynosM5.td | 611 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedThunderX2T99.td | 357 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedThunderX3T110.td | 616 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedNeoverseN2.td | 54 def : ReadAdvance<ReadI, 0>;
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| H A D | AArch64SchedA64FX.td | 756 def : ReadAdvance<ReadI, 0>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 589 auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, in insertComparison() local 592 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) in insertComparison()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | LiveInterval.h | 938 LiveRange::iterator ReadI; variable
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