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Searched refs:ReadAdvance (Results 1 – 25 of 56) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td168 def : ReadAdvance<ReadJmp, 0>;
169 def : ReadAdvance<ReadJalr, 0>;
170 def : ReadAdvance<ReadCSR, 0>;
173 def : ReadAdvance<ReadIALU, 0>;
174 def : ReadAdvance<ReadIALU32, 0>;
179 def : ReadAdvance<ReadIDiv, 0>;
180 def : ReadAdvance<ReadIDiv32, 0>;
181 def : ReadAdvance<ReadIMul, 0>;
182 def : ReadAdvance<ReadIMul32, 0>;
195 def : ReadAdvance<ReadFMA32, 0>;
[all …]
H A DRISCVSchedRocket.td181 def : ReadAdvance<ReadJmp, 0>;
182 def : ReadAdvance<ReadJalr, 0>;
183 def : ReadAdvance<ReadCSR, 0>;
186 def : ReadAdvance<ReadIALU, 0>;
187 def : ReadAdvance<ReadIALU32, 0>;
192 def : ReadAdvance<ReadIDiv, 0>;
193 def : ReadAdvance<ReadIDiv32, 0>;
194 def : ReadAdvance<ReadIMul, 0>;
195 def : ReadAdvance<ReadIMul32, 0>;
208 def : ReadAdvance<ReadFMA32, 0>;
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H A DRISCVScheduleB.td200 def : ReadAdvance<ReadCLZ, 0>;
202 def : ReadAdvance<ReadCTZ, 0>;
204 def : ReadAdvance<ReadCPOP, 0>;
206 def : ReadAdvance<ReadREV8, 0>;
207 def : ReadAdvance<ReadORCB, 0>;
248 def : ReadAdvance<ReadBFP, 0>;
284 def : ReadAdvance<ReadORC, 0>;
285 def : ReadAdvance<ReadREV, 0>;
292 def : ReadAdvance<ReadSHFL, 0>;
300 def : ReadAdvance<ReadPACK, 0>;
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H A DRISCVScheduleV.td691 def : ReadAdvance<ReadVLDX, 0>;
692 def : ReadAdvance<ReadVSTX, 0>;
697 def : ReadAdvance<ReadVSTM, 0>;
698 def : ReadAdvance<ReadVLDSX, 0>;
699 def : ReadAdvance<ReadVSTSX, 0>;
724 def : ReadAdvance<ReadVST1R, 0>;
725 def : ReadAdvance<ReadVST2R, 0>;
726 def : ReadAdvance<ReadVST4R, 0>;
727 def : ReadAdvance<ReadVST8R, 0>;
734 def : ReadAdvance<ReadVExtV, 0>;
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H A DRISCVSchedule.td209 def : ReadAdvance<ReadFALU16, 0>;
210 def : ReadAdvance<ReadFClass16, 0>;
211 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
212 def : ReadAdvance<ReadFCvtF64ToF16, 0>;
219 def : ReadAdvance<ReadFDiv16, 0>;
220 def : ReadAdvance<ReadFCmp16, 0>;
221 def : ReadAdvance<ReadFMA16, 0>;
222 def : ReadAdvance<ReadFMinMax16, 0>;
223 def : ReadAdvance<ReadFMul16, 0>;
226 def : ReadAdvance<ReadFSGNJ16, 0>;
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td106 // These ReadAdvance entries are not used in the Falkor sched model.
107 def : ReadAdvance<ReadI, 0>;
108 def : ReadAdvance<ReadISReg, 0>;
109 def : ReadAdvance<ReadIEReg, 0>;
110 def : ReadAdvance<ReadIM, 0>;
111 def : ReadAdvance<ReadIMA, 0>;
112 def : ReadAdvance<ReadID, 0>;
113 def : ReadAdvance<ReadExtrHi, 0>;
114 def : ReadAdvance<ReadAdrBase, 0>;
115 def : ReadAdvance<ReadVLD, 0>;
[all …]
H A DAArch64SchedKryo.td113 def : ReadAdvance<ReadI, 0>;
114 def : ReadAdvance<ReadISReg, 0>;
115 def : ReadAdvance<ReadIEReg, 0>;
116 def : ReadAdvance<ReadIM, 0>;
117 def : ReadAdvance<ReadIMA, 0>;
118 def : ReadAdvance<ReadID, 0>;
119 def : ReadAdvance<ReadExtrHi, 0>;
120 def : ReadAdvance<ReadAdrBase, 0>;
121 def : ReadAdvance<ReadVLD, 0>;
122 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedThunderX.td194 def : ReadAdvance<ReadExtrHi, 1>;
195 def : ReadAdvance<ReadAdrBase, 2>;
196 def : ReadAdvance<ReadVLD, 2>;
197 def : ReadAdvance<ReadST, 2>;
203 // ReadAdvance applies to Extended registers as well, even though there is
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
229 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
239 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td152 def : ReadAdvance<ReadExtrHi, 0>;
153 def : ReadAdvance<ReadAdrBase, 0>;
154 def : ReadAdvance<ReadST, 0>;
155 def : ReadAdvance<ReadVLD, 0>;
160 // ReadAdvance applies to Extended registers as well, even though there is
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
196 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedTSV110.td110 def : ReadAdvance<ReadI, 0>;
111 def : ReadAdvance<ReadISReg, 0>;
112 def : ReadAdvance<ReadIEReg, 0>;
113 def : ReadAdvance<ReadIM, 0>;
114 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
115 def : ReadAdvance<ReadID, 0>;
116 def : ReadAdvance<ReadExtrHi, 0>;
117 def : ReadAdvance<ReadAdrBase, 0>;
118 def : ReadAdvance<ReadVLD, 0>;
119 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedA55.td210 def : ReadAdvance<ReadVLD, 0>;
211 def : ReadAdvance<ReadExtrHi, 1>;
212 def : ReadAdvance<ReadAdrBase, 1>;
213 def : ReadAdvance<ReadST, 1>;
219 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
243 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
247 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
253 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedExynosM3.td272 def : ReadAdvance<ReadI, 0>;
273 def : ReadAdvance<ReadISReg, 0>;
274 def : ReadAdvance<ReadIEReg, 0>;
275 def : ReadAdvance<ReadIM, 0>;
277 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
278 def : ReadAdvance<ReadID, 0>;
279 def : ReadAdvance<ReadExtrHi, 0>;
280 def : ReadAdvance<ReadAdrBase, 0>;
281 def : ReadAdvance<ReadVLD, 0>;
282 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedCyclone.td187 def : ReadAdvance<ReadExtrHi, 1>;
262 def : ReadAdvance<ReadST, 0>;
638 def : ReadAdvance<ReadVLD, 5>;
868 def : ReadAdvance<ReadI, 0>;
869 def : ReadAdvance<ReadISReg, 0>;
870 def : ReadAdvance<ReadIEReg, 0>;
871 def : ReadAdvance<ReadIM, 0>;
872 def : ReadAdvance<ReadIMA, 0>;
873 def : ReadAdvance<ReadID, 0>;
H A DAArch64SchedAmpere1.td675 def : ReadAdvance<ReadI, 0>;
676 def : ReadAdvance<ReadISReg, 0>;
677 def : ReadAdvance<ReadIEReg, 0>;
678 def : ReadAdvance<ReadIM, 0>;
679 def : ReadAdvance<ReadIMA, 1, [WriteIM32, WriteIM64]>;
680 def : ReadAdvance<ReadID, 0>;
681 def : ReadAdvance<ReadExtrHi, 0>;
682 def : ReadAdvance<ReadST, 0>;
683 def : ReadAdvance<ReadAdrBase, 0>;
684 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedA57.td114 def : ReadAdvance<ReadI, 0>;
115 def : ReadAdvance<ReadISReg, 0>;
116 def : ReadAdvance<ReadIEReg, 0>;
117 def : ReadAdvance<ReadIM, 0>;
118 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
119 def : ReadAdvance<ReadID, 0>;
120 def : ReadAdvance<ReadExtrHi, 0>;
121 def : ReadAdvance<ReadST, 0>;
122 def : ReadAdvance<ReadAdrBase, 0>;
123 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM4.td576 def : ReadAdvance<ReadI, 0>;
577 def : ReadAdvance<ReadISReg, 0>;
578 def : ReadAdvance<ReadIEReg, 0>;
579 def : ReadAdvance<ReadIM, 0>;
581 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
582 def : ReadAdvance<ReadID, 0>;
583 def : ReadAdvance<ReadExtrHi, 0>;
584 def : ReadAdvance<ReadAdrBase, 0>;
585 def : ReadAdvance<ReadVLD, 0>;
586 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedExynosM5.td611 def : ReadAdvance<ReadI, 0>;
612 def : ReadAdvance<ReadISReg, 0>;
613 def : ReadAdvance<ReadIEReg, 0>;
614 def : ReadAdvance<ReadIM, 0>;
616 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
617 def : ReadAdvance<ReadID, 0>;
618 def : ReadAdvance<ReadExtrHi, 0>;
619 def : ReadAdvance<ReadAdrBase, 0>;
620 def : ReadAdvance<ReadVLD, 0>;
621 def : ReadAdvance<ReadST, 0>;
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp524 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
525 if (ReadAdvance < 0) { in collectWrites()
527 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
540 if (ReadAdvance < 0) { in collectWrites()
542 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
582 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in checkRAWHazards() local
593 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRAWHazards()
643 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in addRegisterRead() local
644 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()
651 unsigned ReadAdvance = static_cast<unsigned>( in addRegisterRead() local
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM4.td100 def : ReadAdvance<ReadALU, 0>;
101 def : ReadAdvance<ReadALUsr, 0>;
102 def : ReadAdvance<ReadMUL, 0>;
103 def : ReadAdvance<ReadMAC, 0>;
134 def : ReadAdvance<ReadFPMUL, 0>;
135 def : ReadAdvance<ReadFPMAC, 0>;
H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
175 def : ReadAdvance<ReadALUsr, 0>;
176 def : ReadAdvance<ReadMUL, 0>;
177 def : ReadAdvance<ReadMAC, 1>;
178 def : ReadAdvance<ReadALU, 0>;
179 def : ReadAdvance<ReadFPMUL, 0>;
180 def : ReadAdvance<ReadFPMAC, 3>;
H A DARMScheduleR52.td87 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
89 def : ReadAdvance<ReadMUL, 0>;
90 def : ReadAdvance<ReadMAC, 0>;
127 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
128 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
134 def : ReadAdvance<R52Read_ISS, 0>;
135 def : ReadAdvance<R52Read_EX1, 1>;
136 def : ReadAdvance<R52Read_EX2, 2>;
137 def : ReadAdvance<R52Read_F0, 0>;
138 def : ReadAdvance<R52Read_F1, 1>;
[all …]
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstruction.cpp72 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { in addUser() argument
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
82 Users.emplace_back(User, ReadAdvance); in addUser()
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dm7-negative-readadvance.s5 # ReadAdvance: 0
7 # ReadAdvance: -1
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dmisched-readadvances.mir3 # (ReadAdvance) for the MSY register operand.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td50 def : ReadAdvance<ReadAfterLd, 3>;
51 def : ReadAdvance<ReadAfterVecLd, 3>;
52 def : ReadAdvance<ReadAfterVecXLd, 3>;
53 def : ReadAdvance<ReadAfterVecYLd, 3>;
55 def : ReadAdvance<ReadInt2Fpu, 0>;

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