Home
last modified time | relevance | path

Searched refs:RdHi (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dequal-rdhi-rdlo-diagnostics.s5 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
7 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
9 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
11 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
13 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
15 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
17 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
19 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
21 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
23 @ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.td4276 bits<4> RdHi;
4279 let Inst{19-16} = RdHi;
4288 bits<4> RdHi;
4291 let Inst{19-16} = RdHi;
4361 [(set GPR:$RdLo, GPR:$RdHi,
4414 bits<4> RdHi;
4417 let Inst{19-16} = RdHi;
4424 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4584 (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4641 bits<4> RdHi;
[all …]
H A DARMInstrThumb2.td687 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
688 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
691 bits<4> RdHi;
699 let Inst{11-8} = RdHi;
704 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
706 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
707 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
710 bits<4> RdHi;
718 let Inst{11-8} = RdHi;
2995 [(set rGPR:$RdLo, rGPR:$RdHi,
[all …]
H A DARMInstrFormats.td1016 bits<4> RdHi;
1017 let Inst{19-16} = RdHi;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td515 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch",
517 class cmp_swap_128 : Pseudo<(outs GPR64common:$RdLo, GPR64common:$RdHi,
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8324 unsigned RdHi = Inst.getOperand(0).getReg(); in validateInstruction() local
8326 if(RdHi == RdLo) { in validateInstruction()