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Searched refs:Rcp (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3509 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); in emitReciprocalU64() local
3511 B.buildFMul(S32, Rcp, B.buildFConstant(S32, BitsToFloat(0x5f7ffffc))); in emitReciprocalU64()
3540 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUnsignedDIV_REM64Impl() local
3545 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); in legalizeUnsignedDIV_REM64Impl()
3546 auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1); in legalizeUnsignedDIV_REM64Impl()
3993 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) in legalizeFDIV64() local
3997 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags); in legalizeFDIV64()
3998 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags); in legalizeFDIV64()
H A DAMDGPUCodeGenPrepare.cpp1146 Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty); in expandDivRem32() local
1147 Value *RcpY = Builder.CreateCall(Rcp, {FloatY}); in expandDivRem32()
H A DAMDGPUISelLowering.cpp1738 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64() local
1739 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
H A DSIISelLowering.cpp9118 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
9120 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
9122 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsNVPTX.def331 // Rcp
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td907 // Rcp
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td1008 // Rcp