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Searched refs:Rb (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-vararg.ll25 ; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12]
28 ; ARM: str [[Rb]], [sp, #4]
35 ; THUMB: ldr.w [[Rb:r[0-9]+]], [sp, #12]
37 ; THUMB: str.w [[Rb]], [sp, #4]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dvgather-opt-addr.ll32 define dso_local void @contiguos_vgather_test(i32 %Rb, i32 %mu, i32 %nloops, <32 x i32> %Vv, <64 x …
60 call void @llvm.hexagon.V6.vgathermh.128B(i8* nonnull %0, i32 %Rb, i32 %mu, <32 x i32> %Vv)
61 call void @llvm.hexagon.V6.vgathermw.128B(i8* nonnull %1, i32 %Rb, i32 %mu, <32 x i32> %Vv)
62 call void @llvm.hexagon.V6.vgathermhw.128B(i8* nonnull %2, i32 %Rb, i32 %mu, <64 x i32> %Vvv)
63 …call void @llvm.hexagon.V6.vgathermhq.128B(i8* nonnull %3, <128 x i1> %4, i32 %Rb, i32 %mu, <32 x …
64 …call void @llvm.hexagon.V6.vgathermwq.128B(i8* nonnull %5, <128 x i1> %4, i32 %Rb, i32 %mu, <32 x …
65 …call void @llvm.hexagon.V6.vgathermhwq.128B(i8* nonnull %6, <128 x i1> %4, i32 %Rb, i32 %mu, <64 x…
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() local
95 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(ARC::MOV_cc_ru6), Rb) in expandCTLZ()
103 .addReg(Rb); in expandCTLZ()
/llvm-project-15.0.7/bolt/include/bolt/Core/
H A DDebugData.h672 void setRangeBase(uint64_t Rb) { in setRangeBase() argument
674 RangeBase = Rb; in setRangeBase()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1049 OffsetRange HCE::getOffsetRange(Register Rb, const MachineInstr &MI) const { in getOffsetRange() argument
1058 if (Rb != Register(Op1) || !Op2.isImm()) in getOffsetRange()
1073 Rb != Register(MI.getOperand(BaseP)) || in getOffsetRange()
H A DHexagonPatterns.td885 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
886 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
887 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
888 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td2620 // add Rd, Rb, -imm -> sub Rd, Rn, imm