| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | add-shl-sdiv-to-srem.ll | 7 ; CHECK-NEXT: ret i8 [[RZ]]
18 ; CHECK-NEXT: ret i8 [[RZ]]
29 ; CHECK-NEXT: ret i32 [[RZ]]
42 ; CHECK-NEXT: ret <3 x i8> [[RZ]]
79 ; CHECK-NEXT: ret i32 [[RZ]]
93 ; CHECK-NEXT: ret i32 [[RZ]]
108 ; CHECK-NEXT: ret i32 [[RZ]]
124 ; CHECK-NEXT: ret i32 [[RZ]]
156 ; CHECK-NEXT: ret i8 [[RZ]]
167 ; CHECK-NEXT: ret i32 [[RZ]]
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | fastcc.ll | 202 ; CHECK-TAIL-RZ-NOT: sub sp, sp
203 ; CHECK-TAIL-RZ: nop
204 ; CHECK-TAIL-RZ-NEXT: //NO_APP
207 ; CHECK-TAIL-RZ-NEXT: add sp, sp, #32
210 ; CHECK-TAIL-RZ-NEXT: ret
245 ; CHECK-TAIL-RZ-NOT: sub sp, sp
246 ; CHECK-TAIL-RZ: nop
247 ; CHECK-TAIL-RZ-NEXT: //NO_APP
253 ; CHECK-TAIL-RZ-NEXT: ret
279 ; CHECK-TAIL-RZ: add sp, sp, #32
[all …]
|
| /llvm-project-15.0.7/compiler-rt/test/asan/TestCases/ |
| H A D | alloca_vla_interact.cpp | 22 #define RZ 32 macro
30 top = alloca1 - RZ; in foo()
39 bot = (char *)alloca(i) - RZ; in foo()
|
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats.td | 66 // Format< OP[6] | RZ[5] | SOP[3] | OFFSET[18] >
77 // Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
91 // Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
107 // Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
195 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
236 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
242 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
262 // Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
400 // Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
430 // Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
[all …]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | expand-isel-7.mir | 1 # This file tests the scenario: ISEL RX, RY, RZ, CR (X != 0 && Y != 0, Z != 0)
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 137 RZ, enumerator
|
| /llvm-project-15.0.7/flang/include/flang/Common/ |
| H A D | format.h | 42 L, O, P, RC, RD, RN, RP, RU, RZ, S, SP, SS, T, TL, TR, X, Z, Colon, Slash, in ENUM_CLASS() argument
342 Advance(TokenKind::RZ); in NextToken()
722 case TokenKind::RZ: in Check()
|
| /llvm-project-15.0.7/flang/include/flang/Parser/ |
| H A D | format-specification.h | 91 RZ, enumerator
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXInstPrinter.cpp | 137 case NVPTX::PTXCvtMode::RZ: in printCvtMode()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/ |
| H A D | AddressSanitizer.cpp | 2393 uint64_t RZ = 0; in getRedzoneSizeForGlobal() local
2398 RZ = MinRZ - SizeInBytes; in getRedzoneSizeForGlobal()
2401 RZ = std::max(MinRZ, std::min(kMaxRZ, (SizeInBytes / MinRZ / 4) * MinRZ)); in getRedzoneSizeForGlobal()
2405 RZ += MinRZ - (SizeInBytes % MinRZ); in getRedzoneSizeForGlobal()
2408 assert((RZ + SizeInBytes) % MinRZ == 0); in getRedzoneSizeForGlobal()
2410 return RZ; in getRedzoneSizeForGlobal()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 707 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate() local
710 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); in evaluate()
|
| /llvm-project-15.0.7/flang/lib/Parser/ |
| H A D | io-parsers.cpp | 683 pure(format::ControlEditDesc::Kind::RZ)) ||
|
| H A D | unparse.cpp | 1542 FMT(RZ); in Unparse()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 372 RZ = 3, // Round towards Zero enumerator
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 472 RZ = 3, // Round towards Zero enumerator
|
| /llvm-project-15.0.7/flang/docs/ |
| H A D | f2018-grammar.md | 689 R1319 round-edit-desc -> RU | RD | RZ | RN | RC | RP
|