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Searched refs:RTZ (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h250 RTZ = 1, enumerator
264 case RISCVFPRndMode::RTZ: in roundingModeToString()
280 .Case("rtz", RISCVFPRndMode::RTZ) in stringToRoundingMode()
293 case RISCVFPRndMode::RTZ: in isValidRoundingMode()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmode-register.mir29 # check that the mode is not changed for interp f16 when the mode is already RTZ
96 # check that the mode is changed from RTZ to RTN for F64 instruction
133 # check that the mode is changed from RTZ to RTN for F64 instruction
194 # setreg as RTZ is set in loop
/llvm-project-15.0.7/libclc/generic/lib/shared/
H A Dvstore.cl119 /* RTZ does not produce Inf for large numbers */
185 /* RTZ does not produce Inf for large numbers */
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVBaseInfo.h425 RTZ = 1, enumerator
H A DSPIRVBaseInfo.cpp573 CASE(FPRoundingMode, RTZ) in getFPRoundingModeName()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1812 DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, Subtarget.getXLenVT())); in lowerFP_TO_INT_SAT()
6693 (int(RoundingMode::TowardZero) << 4 * RISCVFPRndMode::RTZ) | in lowerGET_ROUNDING()
6723 (RISCVFPRndMode::RTZ << 4 * int(RoundingMode::TowardZero)) | in lowerSET_ROUNDING()
6861 DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, MVT::i64)); in ReplaceNodeResults()
6869 DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, MVT::i64)); in ReplaceNodeResults()
8487 case ISD::FTRUNC: return RISCVFPRndMode::RTZ; in matchRoundingOp()