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Searched refs:RSC (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DAnalysis.cpp215 ResolvedSchedClass &&RSC) in ResolvedSchedClassAndPoints() argument
216 : RSC(std::move(RSC)) {} in ResolvedSchedClassAndPoints()
303 const ResolvedSchedClass &RSC, raw_ostream &OS) const { in printSchedClassClustersHtml() argument
367 RSC.getAsPoint(Mode, STI, Centroid.getStats()); in measurementsMatch()
385 if (RSC.SCDesc->isValid()) { in printSchedClassDescHtml()
389 OS << "<td>" << RSC.SCDesc->NumMicroOps << "</td>"; in printSchedClassDescHtml()
396 if (RSC.SCDesc->NumWriteLatencyEntries > 1) { in printSchedClassDescHtml()
411 for (const auto &WPR : RSC.NonRedundantWriteProcRes) { in printSchedClassDescHtml()
554 if (!RSCAndPoints.RSC.SCDesc) in run()
590 OS << RSCAndPoints.RSC.SchedClassId; in run()
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H A DAnalysis.h102 explicit ResolvedSchedClassAndPoints(ResolvedSchedClass &&RSC);
104 ResolvedSchedClass RSC; member
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td129 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
H A DARMScheduleA57.td172 // RSB{S}, RSC{S}, SUB{S}, SBC{S}, TEQ, TST
H A DARMInstrInfo.td3867 defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>;
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dbasic-arm-instructions.txt1337 # RSC
/llvm-project-15.0.7/lldb/tools/debugserver/source/
H A DChangeLog257 assembly for "RSC" instruction so this compiles for armv7 (which defaults
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-arm-instructions.s2084 @ RSC