Searched refs:RSB (Results 1 – 15 of 15) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 95 unsigned RSB; member
307 STORE_OPCODE(RSB, RSBri); in OpcodeCache()
886 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB)) in select()
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| H A D | ARMScheduleM7.td | 326 (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
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| H A D | ARMScheduleSwift.td | 129 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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| H A D | ARMScheduleA57.td | 172 // RSB{S}, RSC{S}, SUB{S}, SBC{S}, TEQ, TST
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| H A D | ARMScheduleA9.td | 2299 def :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB
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| H A D | ARMInstrThumb2.td | 2402 // RSB
5114 // Alias for RSB with and without the ".w" optional width specifier, with and
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| H A D | ARMInstrInfo.td | 3859 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | thumb1.txt | 361 # RSB
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| H A D | thumb2.txt | 1545 # RSB (immediate)
1557 # RSB (register)
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| H A D | basic-arm-instructions.txt | 1269 # RSB
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 492 @ RSB
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| H A D | thumb2-narrow-dp.ll | 724 // RSB - only two register version available
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| H A D | basic-thumb2-instructions.s | 2256 @ RSB (immediate)
2278 @ RSB (register)
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| H A D | basic-arm-instructions.s | 1967 @ RSB
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | SpeculativeLoadHardening.md | 191 the case of a filled RSB) and so it is also protected from variant #1 style
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