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Searched refs:RM (Results 1 – 25 of 150) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/LowerMatrixIntrinsics/
H A Dmultiply-i32-row-major.ll8 ; RM-LABEL: @multiply_2x2(
9 ; RM-NEXT: entry:
24 ; RM-NEXT: [[TMP4:%.*]] = add <1 x i32> [[TMP1]], [[TMP3]]
37 ; RM-NEXT: [[TMP11:%.*]] = add <1 x i32> [[TMP8]], [[TMP10]]
67 ; RM-NEXT: ret <4 x i32> [[TMP28]]
77 ; RM-LABEL: @multiply_1x2(
78 ; RM-NEXT: entry:
111 ; RM-NEXT: ret <4 x i32> [[TMP16]]
121 ; RM-LABEL: @multiply_2x3(
122 ; RM-NEXT: entry:
[all …]
H A Dmultiply-add-sub-double-row-major.ll9 ; RM-LABEL: @multiply_sub_add_2x3_3x2(
10 ; RM-NEXT: entry:
11 ; RM-NEXT: [[TMP0:%.*]] = bitcast <6 x double>* [[A_PTR:%.*]] to double*
12 ; RM-NEXT: [[VEC_CAST:%.*]] = bitcast double* [[TMP0]] to <3 x double>*
28 ; RM-NEXT: [[TMP4:%.*]] = bitcast <6 x double>* [[A_PTR]] to double*
56 ; RM-NEXT: [[TMP13:%.*]] = fadd <1 x double> [[TMP10]], [[TMP12]]
62 ; RM-NEXT: [[TMP16:%.*]] = fadd <1 x double> [[TMP13]], [[TMP15]]
75 ; RM-NEXT: [[TMP23:%.*]] = fadd <1 x double> [[TMP20]], [[TMP22]]
81 ; RM-NEXT: [[TMP26:%.*]] = fadd <1 x double> [[TMP23]], [[TMP25]]
94 ; RM-NEXT: [[TMP33:%.*]] = fadd <1 x double> [[TMP30]], [[TMP32]]
[all …]
H A Dtranspose-i32-row-major.ll5 ; RM-LABEL: @transpose(
6 ; RM-NEXT: entry:
9 ; RM-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> [[SPLIT]], i64 0
13 ; RM-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[SPLIT]], i64 1
28 ; RM-NEXT: ret <8 x i32> [[TMP18]]
38 ; RM-LABEL: @transpose_single_column(
39 ; RM-NEXT: entry:
64 ; RM-NEXT: ret <8 x i32> [[TMP15]]
74 ; RM-LABEL: @transpose_i32_3x4(
75 ; RM-NEXT: entry:
[all …]
H A Dtranspose-double-row-major.ll5 ; RM-LABEL: @transpose(
6 ; RM-NEXT: entry:
9 ; RM-NEXT: [[TMP0:%.*]] = extractelement <4 x double> [[SPLIT]], i64 0
13 ; RM-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[SPLIT]], i64 1
28 ; RM-NEXT: ret <8 x double> [[TMP18]]
38 ; RM-LABEL: @transpose_single_column(
39 ; RM-NEXT: entry:
64 ; RM-NEXT: ret <8 x double> [[TMP15]]
74 ; RM-LABEL: @transpose_double_3x4(
75 ; RM-NEXT: entry:
[all …]
H A Dtranspose-float-row-major.ll5 ; RM-LABEL: @transpose(
6 ; RM-NEXT: entry:
9 ; RM-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[SPLIT]], i64 0
13 ; RM-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[SPLIT]], i64 1
28 ; RM-NEXT: ret <8 x float> [[TMP18]]
38 ; RM-LABEL: @transpose_single_column(
39 ; RM-NEXT: entry:
64 ; RM-NEXT: ret <8 x float> [[TMP15]]
74 ; RM-LABEL: @transpose_float_3x4(
75 ; RM-NEXT: entry:
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
58 return RM.value_or(Reloc::Static); in getEffectiveRelocModel()
72 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, in getEffectiveSparcCodeModel() argument
84 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; in getEffectiveSparcCodeModel()
92 const TargetOptions &Options, Optional<Reloc::Model> RM, in SparcTargetMachine() argument
95 getEffectiveRelocModel(RM), in SparcTargetMachine()
97 CM, getEffectiveRelocModel(RM), is64bit, JIT), in SparcTargetMachine()
190 Optional<Reloc::Model> RM, in SparcV8TargetMachine() argument
200 Optional<Reloc::Model> RM, in SparcV9TargetMachine() argument
203 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} in SparcV9TargetMachine()
[all …]
H A DSparcTargetMachine.h30 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
51 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
62 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
72 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DAPFloat.h647 opStatus roundToIntegral(roundingMode RM);
974 return U.IEEE.add(RHS.U.IEEE, RM); in add()
976 return U.Double.add(RHS.U.Double, RM); in add()
983 return U.IEEE.subtract(RHS.U.IEEE, RM); in subtract()
992 return U.IEEE.multiply(RHS.U.IEEE, RM); in multiply()
1001 return U.IEEE.divide(RHS.U.IEEE, RM); in divide()
1003 return U.Double.divide(RHS.U.Double, RM); in divide()
1025 roundingMode RM) { in fusedMultiplyAdd() argument
1034 RM); in fusedMultiplyAdd()
1037 opStatus roundToIntegral(roundingMode RM) { in roundToIntegral() argument
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DFPEnv.h65 inline bool isDefaultFPEnvironment(fp::ExceptionBehavior EB, RoundingMode RM) { in isDefaultFPEnvironment() argument
66 return EB == fp::ebIgnore && RM == RoundingMode::NearestTiesToEven; in isDefaultFPEnvironment()
77 inline bool canRoundingModeBe(RoundingMode RM, RoundingMode QRM) { in canRoundingModeBe() argument
78 return RM == QRM || RM == RoundingMode::Dynamic; in canRoundingModeBe()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZTargetMachine.cpp118 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
121 if (!RM || *RM == Reloc::DynamicNoPIC) in getEffectiveRelocModel()
123 return *RM; in getEffectiveRelocModel()
156 getEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, in getEffectiveSystemZCodeModel() argument
166 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; in getEffectiveSystemZCodeModel()
173 Optional<Reloc::Model> RM, in SystemZTargetMachine() argument
178 getEffectiveRelocModel(RM), in SystemZTargetMachine()
179 getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT), in SystemZTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp108 Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
109 if (!RM || JIT) in getEffectiveRelocModel()
111 return *RM; in getEffectiveRelocModel()
122 Optional<Reloc::Model> RM, in MipsTargetMachine() argument
127 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), in MipsTargetMachine()
150 Optional<Reloc::Model> RM, in MipsebTargetMachine() argument
153 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} in MipsebTargetMachine()
160 Optional<Reloc::Model> RM, in MipselTargetMachine() argument
163 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} in MipselTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp198 Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
199 if (!RM) in getEffectiveRelocModel()
203 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI) in getEffectiveRelocModel()
208 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin()) in getEffectiveRelocModel()
211 return *RM; in getEffectiveRelocModel()
219 Optional<Reloc::Model> RM, in ARMBaseTargetMachine() argument
223 CPU, FS, Options, getEffectiveRelocModel(TT, RM), in ARMBaseTargetMachine()
319 Optional<Reloc::Model> RM, in ARMLETargetMachine() argument
322 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in ARMLETargetMachine()
327 Optional<Reloc::Model> RM, in ARMBETargetMachine() argument
[all …]
/llvm-project-15.0.7/llvm/include/llvm/ExecutionEngine/Orc/
H A DJITTargetMachineBuilder.h86 JITTargetMachineBuilder &setRelocationModel(Optional<Reloc::Model> RM) { in setRelocationModel() argument
87 this->RM = std::move(RM); in setRelocationModel()
92 const Optional<Reloc::Model> &getRelocationModel() const { return RM; } in getRelocationModel()
153 Optional<Reloc::Model> RM; variable
/llvm-project-15.0.7/llvm/lib/Target/
H A DTargetMachineC.cpp102 Optional<Reloc::Model> RM; in LLVMCreateTargetMachine() local
105 RM = Reloc::Static; in LLVMCreateTargetMachine()
108 RM = Reloc::PIC_; in LLVMCreateTargetMachine()
111 RM = Reloc::DynamicNoPIC; in LLVMCreateTargetMachine()
114 RM = Reloc::ROPI; in LLVMCreateTargetMachine()
117 RM = Reloc::RWPI; in LLVMCreateTargetMachine()
120 RM = Reloc::ROPI_RWPI; in LLVMCreateTargetMachine()
146 return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM, CM, in LLVMCreateTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430TargetMachine.cpp29 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
30 return RM.value_or(Reloc::Static); in getEffectiveRelocModel()
41 Optional<Reloc::Model> RM, in MSP430TargetMachine() argument
45 Options, getEffectiveRelocModel(RM), in MSP430TargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCTargetMachine.cpp23 static Reloc::Model getRelocModel(Optional<Reloc::Model> RM) { in getRelocModel() argument
24 return RM.value_or(Reloc::Static); in getRelocModel()
31 Optional<Reloc::Model> RM, in ARCTargetMachine() argument
37 TT, CPU, FS, Options, getRelocModel(RM), in ARCTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiTargetMachine.cpp50 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
51 return RM.value_or(Reloc::PIC_); in getEffectiveRelocModel()
57 Optional<Reloc::Model> RM, in LanaiTargetMachine() argument
61 getEffectiveRelocModel(RM), in LanaiTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVTargetMachine.cpp55 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
56 if (!RM) in getEffectiveRelocModel()
58 return *RM; in getEffectiveRelocModel()
67 Optional<Reloc::Model> RM, in SPIRVTargetMachine() argument
71 getEffectiveRelocModel(RM), in SPIRVTargetMachine()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFRegisters.cpp75 for (const uint32_t *RM : TRI.getRegMasks()) in PhysicalRegisterInfo() local
76 RegMasks.insert(RM); in PhysicalRegisterInfo()
118 for (const uint32_t *RM : RegMasks) { in getAliasSet() local
119 RegisterId MI = getRegMaskId(RM); in getAliasSet()
128 for (const uint32_t *RM : RegMasks) { in getAliasSet() local
129 RegisterId MI = getRegMaskId(RM); in getAliasSet()
167 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { in aliasRM()
168 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
169 const uint32_t *MB = getRegMaskBits(RM.Reg); in aliasRM()
203 assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); in aliasMM()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreTargetMachine.cpp28 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
29 return RM.value_or(Reloc::Static); in getEffectiveRelocModel()
47 Optional<Reloc::Model> RM, in XCoreTargetMachine() argument
52 TT, CPU, FS, Options, getEffectiveRelocModel(RM), in XCoreTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kTargetMachine.cpp73 Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
75 if (!RM.hasValue()) { in getEffectiveRelocModel()
79 return *RM; in getEffectiveRelocModel()
98 Optional<Reloc::Model> RM, in M68kTargetMachine() argument
102 Options, getEffectiveRelocModel(TT, RM), in M68kTargetMachine()
/llvm-project-15.0.7/llvm/test/Linker/
H A Dcomdat-rm-dst.ll3 ; RUN: FileCheck --check-prefix=RM %s < %t
12 ; RM-NOT: @alias =
27 ; RM-NOT: @func()
32 ; RM-NOT: var
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRTargetMachine.cpp40 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
41 return RM.value_or(Reloc::Static); in getEffectiveRelocModel()
47 Optional<Reloc::Model> RM, in AVRTargetMachine() argument
51 getEffectiveRelocModel(RM), in AVRTargetMachine()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVETargetMachine.cpp63 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel() argument
64 return RM.value_or(Reloc::Static); in getEffectiveRelocModel()
82 Optional<Reloc::Model> RM, in VETargetMachine() argument
86 getEffectiveRelocModel(RM), in VETargetMachine()
/llvm-project-15.0.7/llvm/lib/Support/
H A DAPFloat.cpp4310 Status |= z.add(c, RM); in addImpl()
4320 Status |= z.add(aa, RM); in addImpl()
4323 Status |= z.add(c, RM); in addImpl()
4324 Status |= z.add(a, RM); in addImpl()
4327 Status |= z.add(a, RM); in addImpl()
4359 Status |= zz.add(c, RM); in addImpl()
4360 Status |= q.add(z, RM); in addImpl()
4363 Status |= zz.add(q, RM); in addImpl()
4438 auto Ret = add(RHS, RM); in subtract()
4509 Status |= V.add(W, RM); in multiply()
[all …]

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