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/llvm-project-15.0.7/llvm/utils/crosstool/
H A Dcreate-snapshots.sh20 readonly REV="${1:-$(getLatestRevisionFromSVN)}"
25 echo "Running: svn export -r ${REV} ${module}; log in ${log}"
26 svn -q export -r ${REV} ${LLVM_PROJECT_SVN}/${module}/trunk \
30 local tarball="${module}-${REV}.tar.bz2"
/llvm-project-15.0.7/lld/test/ELF/linkerscript/
H A Dmulti-sections-constraint.s20 # RUN: llvm-objdump --section-headers %t2 | FileCheck %s --check-prefix=REV
22 # REV: Sections:
23 # REV-NEXT: Idx Name Size VMA Type
24 # REV: .aaa 00000010 0000000000001000 DATA
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dbitreverse-recognize.ll7 ; CHECK-NEXT: [[REV:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[A:%.*]])
8 ; CHECK-NEXT: ret i32 [[REV]]
32 ; CHECK-NEXT: [[REV:%.*]] = call i64 @llvm.bitreverse.i64(i64 [[TMP0:%.*]])
33 ; CHECK-NEXT: ret i64 [[REV]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-bitcast-bigendian.mir13 ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
14 ; CHECK: $x0 = COPY [[REV]]
/llvm-project-15.0.7/llvm/docs/
H A DBigEndianNEON.rst78 …DR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can simulate either typ…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
133 … to avoid alignment faults (the result of the ``LD1`` would then need to be reversed with ``REV``).
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
161 2. Create code generation patterns for bitconverts that create ``REV`` instructions.
188 …REV`` undoing the ``LD1`` of type ``X`` (converting the in-register representation to the same as …
202 It turns out that these ``REV`` pairs can, in almost all cases, be squashed together into a single …
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbswap.ll382 ; CHECK-NEXT: [[REV:%.*]] = call i16 @llvm.bswap.i16(i16 [[TRUNC]])
383 ; CHECK-NEXT: ret i16 [[REV]]
398 ; CHECK-NEXT: ret <2 x i16> [[REV]]
412 ; CHECK-NEXT: [[REV:%.*]] = call i32 @llvm.bswap.i32(i32 [[TRUNC]])
413 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[REV]] to i64
433 ; CHECK-NEXT: [[REV:%.*]] = call i32 @llvm.bswap.i32(i32 [[TRUNC]])
434 ; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[REV]] to i16
456 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[REV]] to i64
471 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[REV]] to <2 x i64>
501 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[REV]] to i50
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-permute-rev.ll226 ; REV instruction will reverse the order of all elements in the vector.
228 ; the correctness of generated REV instruction for shuffle pattern cannot be guaranteed.
230 ; sve-vector-bits-min=256, sve-vector-bits-max is not set, REV inst can't be generated.
271 ; REV pattern for v32i8 shuffle with vscale_range(2,2)
286 ; REV pattern for v16i16 shuffle with vscale_range(2,2)
301 ; REV pattern for v8f32 shuffle with vscale_range(2,2)
316 ; REV pattern for v4f64 shuffle with vscale_range(2,2)
331 ; REV pattern for shuffle two v8i32 inputs with the second input available, vscale_range(2,2).
347 ; Illegal REV pattern.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM4.td88 "t2(S|Q|SH|U|UQ|UH|QD)(ADD|ASX|SAX|SUB)", "t2USADA8", "(t|t2)REV")>;
H A DARMScheduleM7.td393 (instregex "t2(RBIT|REV)", "tREV")>;
H A DARMScheduleR52.td338 (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>;
H A DARMScheduleSwift.td131 // CLZ,RBIT,REV,REV16,REVSH,PKH
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dthumb1.txt342 # REV/REV16/REVSH
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td318 def REV : Rs<29, "rev", ["s29"]>, DwarfRegNum<[173]>;
388 def S29_28 : Rss<28, "s29:28", [DIAG, REV]>, DwarfRegNum<[172]>;
603 S26, CFGBASE, DIAG, REV, PCYCLEHI,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td410 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
650 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^REV(16|32|64)v")>;
H A DAArch64SchedKryoDetails.td1752 (instregex "REV(16|32)?(W|X)r")>;
1758 (instregex "REV(16|32|64)(v8i8|v4i16|v2i32)")>;
1764 (instregex "REV(16|32|64)(v16i8|v8i16|v4i32)")>;
H A DAArch64SchedFalkorDetails.td919 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^REV(16|32|64)v.*$")>;
1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
H A DAArch64SchedCyclone.td152 // CLS,CLZ,RBIT,REV,REV16,REV32
H A DAArch64SchedExynosM3.td680 def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
H A DAArch64SchedAmpere1.td988 (instregex "(RBIT|REV|REV16)(W|X)r", "REV32Xr")>;
H A DAArch64InstrInfo.td7421 // conversions require one or more REV instructions.
7434 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
7437 // v1 = REV v2i32 (implicit)
7439 // v3 = REV v4i16 v2 (implicit)
7446 // v1 = REV v2i32 (implicit)
7447 // v2 = REV v2i32
7449 // v4 = REV v4i16
7450 // v5 = REV v4i16 v4 (implicit)
7453 // This means an extra two instructions, but actually in most cases the two REV
7457 // There is also no 128-bit REV instruction. This must be synthesized with an
H A DAArch64SchedExynosM4.td829 def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>;
H A DAArch64SchedExynosM5.td864 def : InstRW<[M5WriteNSHF2], (instregex "^REV(16|32|64)v")>;
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s472 @ REV/REV16/REVSH
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp787 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
/llvm-project-15.0.7/polly/lib/External/isl/imath/
H A Dimath.c100 static inline void REV(unsigned char *A, int N) { in REV() function
2772 REV(buf, pos); in s_tobin()

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