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/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dto_addr_builtin.cl20 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
25 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
30 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
35 //CHECK: %{{.*}} = bitcast i8 addrspace(1)* %[[RET]] to i32 addrspace(1)*
40 //CHECK: %{{.*}} = bitcast i8 addrspace(3)* %[[RET]] to i32 addrspace(3)*
45 //CHECK: %{{.*}} = bitcast i8 addrspace(3)* %[[RET]] to i32 addrspace(3)*
50 //CHECK: %{{.*}} = bitcast i8 addrspace(3)* %[[RET]] to i32 addrspace(3)*
60 //CHECK: %{{.*}} = bitcast i8* %[[RET]] to i32*
65 //CHECK: %{{.*}} = bitcast i8* %[[RET]] to i32*
70 //CHECK: %{{.*}} = bitcast i8* %[[RET]] to i32*
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcanonicalize-ashr-shl-to-masking.ll20 ; CHECK-NEXT: ret i8 [[RET]]
41 ; CHECK-NEXT: ret i8 [[RET]]
52 ; CHECK-NEXT: ret i8 [[RET]]
67 ; CHECK-NEXT: ret i8 [[RET]]
77 ; CHECK-NEXT: ret i8 [[RET]]
88 ; CHECK-NEXT: ret i8 [[RET]]
99 ; CHECK-NEXT: ret i8 [[RET]]
114 ; CHECK-NEXT: ret i8 [[RET]]
124 ; CHECK-NEXT: ret i8 [[RET]]
135 ; CHECK-NEXT: ret i8 [[RET]]
[all …]
H A Dcanonicalize-lshr-shl-to-masking.ll20 ; CHECK-NEXT: ret i8 [[RET]]
41 ; CHECK-NEXT: ret i8 [[RET]]
52 ; CHECK-NEXT: ret i8 [[RET]]
67 ; CHECK-NEXT: ret i8 [[RET]]
88 ; CHECK-NEXT: ret i8 [[RET]]
99 ; CHECK-NEXT: ret i8 [[RET]]
114 ; CHECK-NEXT: ret i8 [[RET]]
135 ; CHECK-NEXT: ret i8 [[RET]]
146 ; CHECK-NEXT: ret i8 [[RET]]
161 ; CHECK-NEXT: ret i8 [[RET]]
[all …]
H A Dcanonicalize-shl-lshr-to-masking.ll19 ; CHECK-NEXT: ret i32 [[RET]]
40 ; CHECK-NEXT: ret i32 [[RET]]
51 ; CHECK-NEXT: ret i32 [[RET]]
62 ; CHECK-NEXT: ret i32 [[RET]]
94 ; CHECK-NEXT: ret i32 [[RET]]
104 ; CHECK-NEXT: ret i32 [[RET]]
114 ; CHECK-NEXT: ret i32 [[RET]]
279 ; CHECK-NEXT: ret i32 [[RET]]
292 ; CHECK-NEXT: ret i32 [[RET]]
305 ; CHECK-NEXT: ret i32 [[RET]]
[all …]
H A Dset-lowbits-mask-canonicalize.ll22 ; CHECK-NEXT: ret i32 [[RET]]
33 ; CHECK-NEXT: ret i32 [[RET]]
64 ; CHECK-NEXT: ret i32 [[RET]]
75 ; CHECK-NEXT: ret i32 [[RET]]
106 ; CHECK-NEXT: ret i32 [[RET]]
117 ; CHECK-NEXT: ret i32 [[RET]]
148 ; CHECK-NEXT: ret i32 [[RET]]
159 ; CHECK-NEXT: ret i32 [[RET]]
244 ; CHECK-NEXT: ret i32 [[RET]]
258 ; CHECK-NEXT: ret i32 [[RET]]
[all …]
H A Dmasked-merge-and-of-ors.ll23 ; CHECK-NEXT: ret i32 [[RET]]
71 ; CHECK-NEXT: ret i32 [[RET]]
131 ; CHECK-NEXT: ret i32 [[RET]]
147 ; CHECK-NEXT: ret i32 [[RET]]
163 ; CHECK-NEXT: ret i32 [[RET]]
179 ; CHECK-NEXT: ret i32 [[RET]]
195 ; CHECK-NEXT: ret i32 [[RET]]
211 ; CHECK-NEXT: ret i32 [[RET]]
228 ; CHECK-NEXT: ret i32 [[RET]]
243 ; CHECK-NEXT: ret i32 [[RET]]
[all …]
H A Dexp2-1.ll24 ; LDEXP16-NEXT: ret double [[RET]]
33 ; NOLDEXP-NEXT: ret double [[RET]]
58 ; NOLDEXP-NEXT: ret double [[RET]]
84 ; NOLDEXP-NEXT: ret double [[RET]]
99 ; LDEXP16-NEXT: ret float [[RET]]
104 ; NOLDEXPF-NEXT: ret float [[RET]]
109 ; NOLDEXP-NEXT: ret float [[RET]]
122 ; LDEXP32-NEXT: ret double [[RET]]
127 ; LDEXP16-NEXT: ret double [[RET]]
137 ; NOLDEXP-NEXT: ret double [[RET]]
[all …]
H A Dmasked-merge-or.ll25 ; CHECK-NEXT: ret i32 [[RET]]
73 ; CHECK-NEXT: ret i32 [[RET]]
129 ; CHECK-NEXT: ret i32 [[RET]]
189 ; CHECK-NEXT: ret i32 [[RET]]
205 ; CHECK-NEXT: ret i32 [[RET]]
221 ; CHECK-NEXT: ret i32 [[RET]]
237 ; CHECK-NEXT: ret i32 [[RET]]
253 ; CHECK-NEXT: ret i32 [[RET]]
269 ; CHECK-NEXT: ret i32 [[RET]]
286 ; CHECK-NEXT: ret i32 [[RET]]
[all …]
H A Dmasked-merge-add.ll25 ; CHECK-NEXT: ret i32 [[RET]]
73 ; CHECK-NEXT: ret i32 [[RET]]
129 ; CHECK-NEXT: ret i32 [[RET]]
189 ; CHECK-NEXT: ret i32 [[RET]]
205 ; CHECK-NEXT: ret i32 [[RET]]
221 ; CHECK-NEXT: ret i32 [[RET]]
237 ; CHECK-NEXT: ret i32 [[RET]]
253 ; CHECK-NEXT: ret i32 [[RET]]
269 ; CHECK-NEXT: ret i32 [[RET]]
286 ; CHECK-NEXT: ret i32 [[RET]]
[all …]
H A Dffs-1.ll27 ; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 0)
28 ; GENERIC-NEXT: ret i32 [[RET]]
40 ; GENERIC-NEXT: ret i32 [[RET]]
78 ; GENERIC-NEXT: ret i32 [[RET]]
90 ; GENERIC-NEXT: ret i32 [[RET]]
102 ; GENERIC-NEXT: ret i32 [[RET]]
114 ; GENERIC-NEXT: ret i32 [[RET]]
126 ; GENERIC-NEXT: ret i32 [[RET]]
138 ; GENERIC-NEXT: ret i32 [[RET]]
164 ; GENERIC-NEXT: ret i32 [[RET]]
[all …]
H A Dmemrchr.ll9 ; CHECK-NEXT: [[RET:%.*]] = call i8* @memrchr(i8* [[STR:%.*]], i32 [[C:%.*]], i32 [[N:%.*]])
10 ; CHECK-NEXT: ret i8* [[RET]]
19 ; CHECK-NEXT: [[RET:%.*]] = call i8* @memrchr(i8* nonnull [[STR:%.*]], i32 [[C:%.*]], i32 [[N:%.…
20 ; CHECK-NEXT: ret i8* [[RET]]
29 ; CHECK-NEXT: [[RET:%.*]] = call i8* @memrchr(i8* [[STR:%.*]], i32 [[C:%.*]], i32 5)
30 ; CHECK-NEXT: ret i8* [[RET]]
39 ; CHECK-NEXT: [[RET:%.*]] = call i8* @memrchr(i8* [[STR:%.*]], i32 [[C:%.*]], i32 5)
40 ; CHECK-NEXT: ret i8* [[RET]]
49 ; CHECK-NEXT: [[RET:%.*]] = call i8* @memrchr(i8* [[STR:%.*]], i32 [[C:%.*]], i32 0)
50 ; CHECK-NEXT: ret i8* [[RET]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dglobal_atomics_i64.ll18 ; CIVI: buffer_store_dwordx2 [[RET]]
44 ; CIVI: buffer_store_dwordx2 [[RET]]
67 ; CIVI: buffer_store_dwordx2 [[RET]]
91 ; CIVI: buffer_store_dwordx2 [[RET]]
114 ; CIVI: buffer_store_dwordx2 [[RET]]
140 ; CIVI: buffer_store_dwordx2 [[RET]]
163 ; CIVI: buffer_store_dwordx2 [[RET]]
187 ; CIVI: buffer_store_dwordx2 [[RET]]
210 ; CIVI: buffer_store_dwordx2 [[RET]]
236 ; CIVI: buffer_store_dwordx2 [[RET]]
[all …]
H A Dglobal_atomics.ll57 ; SIVI: buffer_store_dword [[RET]]
83 ; SIVI: buffer_store_dword [[RET]]
107 ; SIVI: buffer_store_dword [[RET]]
132 ; SIVI: buffer_store_dword [[RET]]
156 ; SIVI: buffer_store_dword [[RET]]
183 ; SIVI: buffer_store_dword [[RET]]
207 ; SIVI: buffer_store_dword [[RET]]
232 ; SIVI: buffer_store_dword [[RET]]
256 ; SIVI: buffer_store_dword [[RET]]
283 ; SIVI: buffer_store_dword [[RET]]
[all …]
H A Dflat_atomics.ll37 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
60 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
80 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
99 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
121 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
144 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
164 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
183 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
205 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
228 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
[all …]
H A Dflat_atomics_i64.ll15 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
36 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
56 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
75 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
95 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
116 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
136 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
155 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
175 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
196 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-ext.mir124 RET 0, implicit $al
157 RET 0, implicit $ax
191 RET 0, implicit $eax
219 RET 0, implicit $ax
247 RET 0, implicit $eax
275 RET 0, implicit $eax
301 RET 0, implicit $al
327 RET 0, implicit $ax
382 RET 0, implicit $ax
468 RET 0, implicit $al
[all …]
H A Dselect-constant.mir51 ; CHECK: RET 0, implicit $al
54 RET 0, implicit $al
69 ; CHECK: RET 0, implicit $ax
72 RET 0, implicit $ax
90 RET 0, implicit $eax
107 RET 0, implicit $eax
125 RET 0, implicit $rax
144 RET 0, implicit $rax
162 RET 0, implicit $rax
181 ; CHECK: RET 0
[all …]
H A Dselect-ext.mir79 RET 0, implicit $al
116 RET 0, implicit $ax
153 RET 0, implicit $eax
182 RET 0, implicit $eax
211 RET 0, implicit $eax
240 RET 0, implicit $eax
269 RET 0, implicit $eax
300 RET 0, implicit $al
332 RET 0, implicit $ax
364 RET 0, implicit $eax
[all …]
H A Dselect-memop-scalar.mir137 RET 0, implicit $al
175 RET 0, implicit $ax
213 RET 0, implicit $eax
251 RET 0, implicit $rax
494 RET 0, implicit $rax
537 RET 0, implicit $rax
817 ; SSE: RET 0
822 ; AVX: RET 0
827 ; AVX512F: RET 0
832 ; AVX512VL: RET 0
[all …]
H A Dlegalize-ext-x86-64.mir91 RET 0, implicit $rax
114 RET 0, implicit $rax
137 RET 0, implicit $rax
160 RET 0, implicit $rax
187 RET 0, implicit $rax
210 RET 0, implicit $rax
233 RET 0, implicit $rax
256 RET 0, implicit $rax
281 RET 0, implicit $rax
304 RET 0, implicit $rax
[all …]
H A Dselect-memop-scalar-unordered.mir137 RET 0, implicit $al
175 RET 0, implicit $ax
213 RET 0, implicit $eax
251 RET 0, implicit $rax
494 RET 0, implicit $rax
537 RET 0, implicit $rax
817 ; SSE: RET 0
822 ; AVX: RET 0
827 ; AVX512F: RET 0
832 ; AVX512VL: RET 0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbranchfolding-debug-invariant.mir13 ; CHECK-NOT: RET
16 ; CHECK: RET 0
24 RET 0
28 RET 0
45 ; CHECK-NOT: RET
58 RET 0
64 RET 0
92 RET 0
97 RET 0
127 RET 0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dpotential.ll35 ; IS__CGSCC_OPM-NEXT: ret i1 [[RET]]
42 ; IS__CGSCC_NPM-NEXT: ret i1 [[RET]]
64 ; CHECK-NEXT: ret i32 [[RET]]
79 ; IS__TUNIT_OPM-NEXT: ret i32 [[RET]]
398 ; CHECK-NEXT: ret i32 [[RET]]
411 ; CHECK-NEXT: ret i32 [[RET]]
424 ; CHECK-NEXT: ret i32 [[RET]]
807 ; CHECK-NEXT: ret i32 [[RET]]
909 ; CHECK-NEXT: ret i1 [[RET]]
926 ; CHECK-NEXT: ret i1 [[RET]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dconstantfold-shl-nuw-C-to-C.ll48 ; CHECK-NEXT: ret i8 [[RET]]
61 ; CHECK-NEXT: ret i8 [[RET]]
104 ; CHECK-NEXT: ret i8 [[RET]]
114 ; CHECK-NEXT: ret i8 [[RET]]
123 ; CHECK-NEXT: ret i8 [[RET]]
134 ; CHECK-NEXT: ret i8 [[RET]]
145 ; CHECK-NEXT: ret i8 [[RET]]
167 ; CHECK-NEXT: ret i8 [[RET]]
180 ; CHECK-NEXT: ret i8 [[RET]]
193 ; CHECK-NEXT: ret i8 [[RET]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dpost-ra-machine-sink.mir25 RET $x0
29 RET $x0
52 RET $x0
57 RET $x0
82 RET $x0
111 RET $x0
116 RET $x0
140 RET $x0
149 RET $x0
173 RET $x0
[all …]

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