Home
last modified time | relevance | path

Searched refs:RESULT (Results 1 – 25 of 217) sorted by relevance

123456789

/llvm-project-15.0.7/llvm/test/tools/llvm-reduce/mir/
H A Dpreserve-machine-function-info-amdgpu.mir7 # RESULT: name: func
16 # RESULT: machineFunctionInfo:
18 # RESULT-NEXT: maxKernArgAlign: 32
19 # RESULT-NEXT: ldsSize: 256
20 # RESULT-NEXT: gdsSize: 128
21 # RESULT-NEXT: dynLDSAlign: 16
33 # RESULT-NEXT: argumentInfo:
46 # RESULT-NEXT: mode:
55 # RESULT-NEXT: wwmReservedRegs:
56 # RESULT-NEXT: - '$vgpr2'
[all …]
H A Dpreserve-frame-info.mir7 # RESULT: frameInfo:
10 # RESULT-NEXT: hasStackMap: true
11 # RESULT-NEXT: hasPatchPoint: true
12 # RESULT-NEXT: offsetAdjustment: 128
13 # RESULT-NEXT: maxAlignment: 64
14 # RESULT-NEXT: adjustsStack: true
15 # RESULT-NEXT: hasCalls: true
17 # RESULT-NEXT: maxCallFrameSize: 420
26 # RESULT-NEXT: fixedStack:
34 # RESULT-NEXT: stack:
[all …]
H A Dpreserve-func-info.mir8 # RESULT: name: func
9 # RESULT-NEXT: alignment: 32
11 # RESULT-NEXT: legalized: true
12 # RESULT-NEXT: regBankSelected: true
13 # RESULT-NEXT: selected: true
14 # RESULT-NEXT: failedISel: true
17 # RESULT-NEXT: callsEHReturn: true
19 # RESULT-NEXT: hasEHCatchret: true
20 # RESULT-NEXT: hasEHScopes: true
21 # RESULT-NEXT: hasEHFunclets: true
[all …]
H A Dpreserve-block-info.mir8 # RESULT: bb.0.entry:
11 # RESULT: bb.1 (address-taken, align 8):
12 # RESULT: bb.2 (landing-pad, align 16):
13 # RESULT: bb.3 (inlineasm-br-indirect-target):
14 # RESULT: bb.4 (ehfunclet-entry):
15 # RESULT: bb.5 (bbsections 1):
16 # RESULT: bb.6 (bbsections 2):
17 # RESULT: bb.7 (bbsections 3):
18 # RESULT: bb.8:
20 # RESULT: bb.9:
[all …]
H A Dreduce-instruction-flags.mir3 # RUN: FileCheck --check-prefix=RESULT %s < %t
13 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
14 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
15 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
16 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
17 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
18 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
19 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
20 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
21 # RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
[all …]
H A Dreduce-instruction-unreachable-block.mir3 # RUN: FileCheck --check-prefix=RESULT %s < %t
9 # RESULT: bb.0:
11 # RESULT: %{{[0-9]+}}:vgpr_32 = IMPLICIT_DEF
12 # RESULT-NEXT: %{{[0-9]+}}:sreg_64 = IMPLICIT_DEF
13 # RESULT-NEXT: %{{[0-9]+}}:vreg_64 = IMPLICIT_DEF
14 # RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
15 # RESULT-NEXT: S_BRANCH %bb.3
17 # RESULT: bb.1:
18 # RESULT-NEXT: S_BRANCH %bb.3
20 # RESULT: bb.2:
[all …]
H A Ddrop-ir-references.mir3 # RUN: FileCheck --check-prefix=RESULT %s < %t
13 # RESULT: name: func
14 # RESULT: stack:
15 # RESULT-NEXT: - { id: 0, size: 32, alignment: 8 }
17 # RESULT: body:
18 # RESULT-NEXT: bb.0:
21 # RESULT: bb.1:
22 # RESULT-NEXT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>), addrspace 3)
27 # RESULT: bb.2:
31 # RESULT: bb.3:
[all …]
H A Dreduce-register-uses.mir3 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
12 # RESULT: %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, undef %vgpr1, implicit $mode, implicit $exec
13 # RESULT: %mul1:vgpr_32 = V_MUL_F32_e32 undef %vgpr1, %vgpr0, implicit $mode, implicit $exec
14 # RESULT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
15 # RESULT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
18 # RESULT: %impdef:vreg_64 = IMPLICIT_DEF
19 # RESULT: GLOBAL_STORE_DWORD undef %ptr, undef %impdef.sub1, 0, 0, implicit $exec
20 # RESULT: undef %impdef.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
21 # RESULT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
22 # RESULT: S_BARRIER
[all …]
H A Dgeneric-vreg.mir3 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
17 # RESULT: %{{[0-9]+}}:vgpr(s32) = G_IMPLICIT_DEF
18 # RESULT-NEXT: %{{[0-9]+}}:vreg_64(s64) = IMPLICIT_DEF
19 # RESULT-NEXT: %{{[0-9]+}}:_(<2 x s32>) = G_IMPLICIT_DEF
20 # RESULT-NEXT: %v1:vgpr(<2 x s16>) = G_IMPLICIT_DEF
21 # RESULT-NEXT: %unused_load_ptr:sgpr(p1) = G_IMPLICIT_DEF
22 # RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %{{[0-9]+}}(<2 x s32>)
23 # RESULT-NEXT: S_NOP 0, implicit %unused_load_ptr(p1)
24 # RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
25 # RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
[all …]
H A Dpreserve-machine-function-info-riscv.mir3 # RUN: FileCheck --check-prefix=RESULT %s < %t
7 # RESULT: name: func
8 # RESULT: stack:
9 # RESULT-NEXT: - { id: 0, offset: 16, size: 16, alignment: 8 }
11 # RESULT: machineFunctionInfo:
12 # RESULT-NEXT: varArgsFrameIndex: 4
13 # RESULT-NEXT: varArgsSaveSize: 12
15 # RESULT: $x10 = ADDW %stack.0, renamable $x10
H A Dpreserve-mem-operands.mir3 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
21 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1, …
22 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1 +…
24 # RESULT: G_STORE %{{[0-9]+}}(<2 x s32>), %{{[0-9]+}}(p3) :: (store (<2 x s32>) into %fixed-stack.0…
25 # RESULT: G_STORE %{{[0-9]+}}(<2 x s32>), %{{[0-9]+}}(p3) :: (store (<2 x s32>) into %stack.0, addr…
26 # RESULT: G_STORE %{{[0-9]+}}(p3), %{{[0-9]+}}(p3) :: (store (p3), addrspace 5)
27 # RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (load (s32) from call-entry @foo, addrspac…
28 # RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p1) :: (load (s32) from constant-pool, addrspace …
29 # RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p0) :: (load (p1) from got, addrspace 4)
30 # RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p0) :: (load (p1) from jump-table, addrspace 4)
[all …]
H A Dpreserve-reg-hints.mir3 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
9 # RESULT: registers:
10 # RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
11 # RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '' }
12 # RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
13 # RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4' }
14 # RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3' }
H A Dreduce-register-hints.mir3 # RUN: FileCheck --check-prefix=RESULT %s < %t
9 # RESULT: registers:
10 # RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
11 # RESULT-NEXT: - { id: 1, class: vgpr_32 }
12 # RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
13 # RESULT-NEXT: - { id: 3, class: vgpr_32 }
14 # RESULT-NEXT: - { id: 4, class: vgpr_32 }
H A Dtracks-reg-liveness.mir3 # RUN: FileCheck --check-prefix=RESULT %s < %t
11 # RESULT: bb.0:
12 # RESULT-NEXT: liveins: $vgpr0, $vgpr1_vgpr2
13 # RESULT: %0:vgpr_32 = V_MOV_B32_e32 $vgpr0, implicit $exec
14 # RESULT-NEXT: S_NOP 0
15 # RESULT-NEXT: S_ENDPGM 0, implicit %0, implicit %0
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dctlz.ll12 ; CHECK: cpi [[RESULT:r[0-9]+]], 0
16 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
17 ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
18 ; CHECK: lsr {{.*}}[[RESULT]]
19 ; CHECK: lsr {{.*}}[[RESULT]]
27 ; CHECK: lsr {{.*}}[[RESULT]]
28 ; CHECK: andi {{.*}}[[RESULT]], 85
31 ; CHECK: andi {{.*}}[[RESULT]], 51
37 ; CHECK: swap {{.*}}[[RESULT]]
39 ; CHECK: andi {{.*}}[[RESULT]], 15
[all …]
H A Dcttz.ll12 ; CHECK: cpi [[RESULT:r[0-9]+]], 0
14 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
16 ; CHECK: com {{.*}}[[RESULT]]
17 ; CHECK: and {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
18 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
21 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
24 ; CHECK: lsr {{.*}}[[RESULT]]
25 ; CHECK: lsr {{.*}}[[RESULT]]
26 ; CHECK: andi {{.*}}[[RESULT]], 51
[all …]
H A Dctpop.ll12 ; CHECK: mov [[SCRATCH:r[0-9]+]], [[RESULT:r[0-9]+]]
15 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
16 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
18 ; CHECK: lsr {{.*}}[[RESULT]]
19 ; CHECK: lsr {{.*}}[[RESULT]]
20 ; CHECK: andi {{.*}}[[RESULT]], 51
21 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
24 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
25 ; CHECK: andi {{.*}}[[RESULT]], 15
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfmuladd.f16.ll119 ; GFX10-FLUSH: global_store_short v{{[0-9]+}}, [[RESULT]]
188 ; GFX10-FLUSH: global_store_short v{{[0-9]+}}, [[RESULT]]
219 ; GFX10-FLUSH: global_store_short v{{[0-9]+}}, [[RESULT]]
277 ; GFX10-FLUSH: global_store_short v{{[0-9]+}}, [[RESULT]]
302 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
305 ; GFX10: global_store_short v{{[0-9]+}}, [[RESULT]]
334 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
338 ; GFX10: global_store_short v{{[0-9]+}}, [[RESULT]]
368 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
372 ; GFX10: global_store_short v{{[0-9]+}}, [[RESULT]]
[all …]
H A Dfmuladd.f32.ll104 ; SI-DENORM: buffer_store_dword [[RESULT]]
135 ; SI-DENORM: buffer_store_dword [[RESULT]]
168 ; SI-DENORM: buffer_store_dword [[RESULT]]
204 ; SI-DENORM: buffer_store_dword [[RESULT]]
323 ; SI-FLUSH: buffer_store_dword [[RESULT]]
363 ; SI: buffer_store_dword [[RESULT]]
398 ; SI: buffer_store_dword [[RESULT]]
432 ; SI: buffer_store_dword [[RESULT]]
468 ; SI: buffer_store_dword [[RESULT]]
542 ; SI: buffer_store_dword [[RESULT]]
[all …]
H A Dtrunc-cmp-constant.ll27 ; SI: buffer_store_byte [[RESULT]]
38 ; SI: buffer_store_byte [[RESULT]]
50 ; SI: buffer_store_byte [[RESULT]]
62 ; SI: buffer_store_byte [[RESULT]]
73 ; SI: buffer_store_byte [[RESULT]]
86 ; SI: buffer_store_byte [[RESULT]]
98 ; SI: buffer_store_byte [[RESULT]]
109 ; SI: buffer_store_byte [[RESULT]]
124 ; SI: buffer_store_byte [[RESULT]]
139 ; XSI-NEXT: buffer_store_byte [[RESULT]]
[all …]
H A Dsetcc-opt.ll10 ; GCN-NEXT:buffer_store_byte [[RESULT]]
28 ; GCN-NEXT: buffer_store_byte [[RESULT]]
46 ; GCN-NEXT: buffer_store_byte [[RESULT]]
61 ; GCN-NEXT: buffer_store_byte [[RESULT]]
76 ; GCN-NEXT: buffer_store_byte [[RESULT]]
170 ; GCN: buffer_store_byte [[RESULT]]
183 ; GCN: buffer_store_byte [[RESULT]]
215 ; GCN: buffer_store_byte [[RESULT]]
226 ; GCN: buffer_store_byte [[RESULT]]
237 ; GCN: buffer_store_byte [[RESULT]]
[all …]
H A Dllvm.amdgcn.ds.consume.ll9 ; GCN: ds_consume [[RESULT:v[0-9]+]]{{$}}
11 ; GCN: {{.*}}store{{.*}} [[RESULT]]
23 ; GCN: {{.*}}store{{.*}} [[RESULT]]
36 ; SI: ds_consume [[RESULT:v[0-9]+]]{{$}}
42 ; GCN: {{.*}}store{{.*}} [[RESULT]]
58 ; GCN: ds_consume [[RESULT:v[0-9]+]]{{$}}
60 ; GCN: {{.*}}store{{.*}} [[RESULT]]
71 ; GCN: ds_consume [[RESULT:v[0-9]+]]{{$}}
73 ; GCN: {{.*}}store{{.*}} [[RESULT]]
85 ; GCN: {{.*}}store{{.*}} [[RESULT]]
[all …]
H A Dconstant-fold-mi-operands.ll5 ; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
6 ; GCN-NOT: [[RESULT]]
7 ; GCN: buffer_store_dword [[RESULT]]
18 ; GCN-NOT: [[RESULT]]
19 ; GCN: buffer_store_dword [[RESULT]]
29 ; GCN-NOT: [[RESULT]]
30 ; GCN: buffer_store_dword [[RESULT]]
54 ; GCN-NOT: [[RESULT]]
55 ; GCN: buffer_store_dword [[RESULT]]
79 ; GCN-NOT: [[RESULT]]
[all …]
H A Dllvm.amdgcn.ds.append.ll9 ; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
11 ; GCN: {{.*}}store{{.*}} [[RESULT]]
23 ; GCN: {{.*}}store{{.*}} [[RESULT]]
36 ; SI: ds_append [[RESULT:v[0-9]+]]{{$}}
42 ; GCN: {{.*}}store{{.*}} [[RESULT]]
61 ; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
63 ; GCN: {{.*}}store{{.*}} [[RESULT]]
77 ; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
79 ; GCN: {{.*}}store{{.*}} [[RESULT]]
91 ; GCN: {{.*}}store{{.*}} [[RESULT]]
[all …]
H A Dllvm.amdgcn.rcp.ll36 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
37 ; SI-NOT: [[RESULT]]
38 ; SI: buffer_store_dword [[RESULT]]
46 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
47 ; SI-NOT: [[RESULT]]
48 ; SI: buffer_store_dword [[RESULT]]
83 ; SI-NOT: [[RESULT]]
84 ; SI: buffer_store_dwordx2 [[RESULT]]
93 ; SI-NOT: [[RESULT]]
94 ; SI: buffer_store_dwordx2 [[RESULT]]
[all …]

123456789