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/llvm-project-15.0.7/llvm/utils/release/
H A Dbuild_llvm_release.bat19 REM Note:
43 REM Prerequisites:
44 REM
49 REM
50 REM
105 REM Preserve original path
117 REM Restore original path
122 REM Set Python environment
159 REM with forward slash.
188 REM Restore original path
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsrem-via-sdiv-mul-sub.ll22 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
23 ; CHECK-NEXT: ret i8 [[REM]]
37 ; CHECK-NEXT: [[REM:%.*]] = sub <2 x i8> [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
38 ; CHECK-NEXT: ret <2 x i8> [[REM]]
55 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
56 ; CHECK-NEXT: ret i8 [[REM]]
76 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
77 ; CHECK-NEXT: ret i8 [[REM]]
95 ; CHECK-NEXT: ret i8 [[REM]]
109 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
[all …]
H A Durem-via-udiv-mul-sub.ll22 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
23 ; CHECK-NEXT: ret i8 [[REM]]
37 ; CHECK-NEXT: [[REM:%.*]] = sub <2 x i8> [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
38 ; CHECK-NEXT: ret <2 x i8> [[REM]]
55 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
56 ; CHECK-NEXT: ret i8 [[REM]]
76 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
77 ; CHECK-NEXT: ret i8 [[REM]]
95 ; CHECK-NEXT: ret i8 [[REM]]
109 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[X]], [[ROUNDXDOWNTOMULTIPLEOFY]]
[all …]
H A Dicmp-mul-and.ll125 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
126 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
138 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 12
139 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
151 ; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
152 ; CHECK-NEXT: ret i32 [[REM]]
174 ; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 4>
175 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
188 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
201 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
[all …]
H A D2009-06-16-SRemDemandedBits.ll8 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X:%.*]], 2
9 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[REM]], 2
H A Dpr36362.ll8 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[C:%.*]], [[SEL1]]
9 ; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[A]], i32 [[REM]], i32 0
H A D2010-01-28-NegativeSRem.ll11 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X]], 2
12 ; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[REM]], -1
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dunroll-pragmas.ll178 ; REM: store
179 ; REM: store
180 ; REM: store
184 ; REM: store
188 ; REM: br i1
282 ; REM: store
284 ; REM: br i1
315 ; REM: store
316 ; REM: store
320 ; REM: store
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dsigned-div-rem.ll177 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[CONV]], 128
178 ; CHECK-NEXT: ret i32 [[REM]]
199 ; CHECK-NEXT: ret i32 [[REM]]
220 ; CHECK-NEXT: ret i32 [[REM]]
241 ; CHECK-NEXT: ret i32 [[REM]]
261 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[AND]], 253
262 ; CHECK-NEXT: ret i32 [[REM]]
283 ; CHECK-NEXT: ret i32 [[REM]]
303 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[OR]], 253
304 ; CHECK-NEXT: ret i32 [[REM]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/DivRemPairs/X86/
H A Ddiv-rem-pairs.ll8 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
10 ; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
22 ; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A]], [[B]]
23 ; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
40 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
69 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[REM]], 42
97 ; CHECK-NEXT: [[REM:%.*]] = srem i16 [[A]], [[B]]
126 ; CHECK-NEXT: [[REM:%.*]] = urem i8 [[A]], [[B]]
198 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
227 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
[all …]
H A Ddiv-expanded-rem-pair.ll151 ; CHECK-NEXT: [[REM:%.*]] = sub i128 [[A]], [[T0]]
214 ; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A]], [[B]]
217 ; CHECK-NEXT: store i64 [[REM]], i64* [[RP]], align 4
272 ; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A]], [[B]]
278 ; CHECK-NEXT: store i64 [[REM]], i64* [[RP:%.*]], align 4
303 ; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A]], [[B]]
342 ; CHECK-NEXT: store i64 [[REM]], i64* [[RP]], align 4
372 ; CHECK-NEXT: store i64 [[REM]], i64* [[RP]], align 4
404 ; CHECK-NEXT: store i128 [[REM]], i128* [[RP]], align 4
434 ; CHECK-NEXT: store i128 [[REM]], i128* [[RP]], align 4
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Ddiv-rem-pairs.ll11 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
12 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
38 ; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A:%.*]], [[B:%.*]]
39 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[REM]], 42
69 ; CHECK-NEXT: [[REM:%.*]] = srem i16 [[A]], [[B]]
72 ; CHECK-NEXT: [[RET:%.*]] = phi i16 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
96 ; CHECK-NEXT: [[REM:%.*]] = urem i8 [[A]], [[B]]
99 ; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dzmmul.ll6 ; RUN: | not FileCheck -check-prefix=CHECK-REM %s
8 ; RUN: | not FileCheck -check-prefix=CHECK-REM %s
25 ; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
27 ; RUN: | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
38 ; CHECK-REM: rem{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
/llvm-project-15.0.7/llvm/test/Transforms/DivRemPairs/PowerPC/
H A Ddiv-expanded-rem-pair.ll10 ; CHECK-NEXT: [[REM:%.*]] = sub i32 [[A]], [[T0]]
11 ; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
25 ; CHECK-NEXT: [[REM:%.*]] = sub i32 [[A]], [[T0]]
26 ; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
46 ; CHECK-NEXT: [[REM:%.*]] = sub i16 [[A]], [[T0]]
49 ; CHECK-NEXT: [[RET:%.*]] = phi i16 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
77 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[A]], [[T0]]
80 ; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
156 ; CHECK-NEXT: [[REM:%.*]] = sub i128 [[A]], [[T0]]
159 ; CHECK-NEXT: [[RET:%.*]] = phi i128 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
H A Ddiv-rem-pairs.ll220 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
221 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
249 ; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A:%.*]], [[B:%.*]]
250 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
278 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
279 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
345 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A]], [[B]]
348 ; CHECK-NEXT: [[RET:%.*]] = phi i32 [ [[DIV]], [[IF]] ], [ [[REM]], [[ELSE]] ]
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Ddfdiv.S90 #define REM r1:0 macro
154 REM = asl(REM,# ## ( REMSHIFT )); \
158 REM -= mpyu(PRODHI,DENOMLO); \
163 REM -= asl(REMSUB2, # ## 32); \
181 TMPPAIR = sub(REM,DENOM)
182 P_TMP = cmp.gtu(DENOM,REM)
188 if (!P_TMP) REM = TMPPAIR
192 P_TMP = cmp.eq(REM,TMPPAIR)
201 #undef REM
/llvm-project-15.0.7/llvm/test/Transforms/DivRemPairs/Mips/
H A Ddiv-rem-pairs.ll8 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
10 ; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
22 ; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A]], [[B]]
23 ; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
38 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
40 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
206 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
207 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
236 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
265 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
[all …]
H A Ddiv-expanded-rem-pair.ll46 ; CHECK-NEXT: [[REM:%.*]] = sub i16 [[A]], [[T0]]
49 ; CHECK-NEXT: [[RET:%.*]] = phi i16 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
77 ; CHECK-NEXT: [[REM:%.*]] = sub i8 [[A]], [[T0]]
80 ; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
151 ; CHECK-NEXT: [[REM:%.*]] = sub i128 [[A]], [[T0]]
154 ; CHECK-NEXT: [[RET:%.*]] = phi i128 [ [[REM]], [[IF]] ], [ 3, [[ENTRY:%.*]] ]
/llvm-project-15.0.7/llvm/test/Transforms/HardwareLoops/ARM/
H A Dfp-emulation.ll14 ; CHECK-FP: [[REM:%[^ ]+]] = phi i32 [ [[START]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.e…
15 ; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
63 ; CHECK-FP: [[REM:%[^ ]+]] = phi i32 [ [[START]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.e…
64 ; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
114 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[START]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.end4…
115 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
165 ; CHECK-FP: [[REM:%[^ ]+]] = phi i32 [ [[START]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.e…
166 ; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
H A Dsimple-do.ll14 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[START]], %entry ], [ [[LOOP_DEC:%[^ ]+]], %while.body ]
15 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
57 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[TEST0]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %while.b…
58 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
107 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[START]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %while…
108 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
160 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[START]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %while.b…
161 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
H A Ddo-rem.ll16 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[TEST0]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %whi…
17 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
57 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[TEST0]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %whi…
58 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
98 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[TEST0]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %whi…
99 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
139 ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[TEST0]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %whi…
140 ; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1)
/llvm-project-15.0.7/llvm/test/Other/X86/
H A Ddebugcounter-divrempairs.ll11 ; CHECK-NEXT: [[REM:%.*]] = urem i64 %a, %b
12 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[REM]], 42
69 ; CHECK-NEXT: [[REM:%.*]] = srem i32 %a, %b
70 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A DoptimizeSelect-DT.ll14 ; CHECK-NEXT: [[REM:%.*]] = srem i32 [[X:%.*]], 2
17 ; CHECK-NEXT: [[MUL:%.*]] = phi i32 [ [[REM]], [[SELECT_TRUE_SINK]] ], [ 0, [[ENTRY:%.*]] ]
/llvm-project-15.0.7/clang/test/SemaObjC/
H A Ddefault-synthesize.m20 @property (nonatomic) int howMany; // REM: nonatomic to avoid warnings about only implementing one…
42 @property (nonatomic) int howMany; // REM: nonatomic to avoid warnings about only implementing one…
71 @synthesize howMany, what; // REM: Redundant anyway
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/ARM/
H A Darm_fill_q7.ll24 ; OLDPM-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3
25 ; OLDPM-NEXT: [[CMP14_NOT17:%.*]] = icmp eq i32 [[REM]], 0
28 … void @llvm.memset.p0i8.i32(i8* align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false)
44 ; NEWPM-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3
45 ; NEWPM-NEXT: [[CMP14_NOT20:%.*]] = icmp eq i32 [[REM]], 0
48 … void @llvm.memset.p0i8.i32(i8* align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false)

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