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/llvm-project-15.0.7/polly/test/ScheduleOptimizer/
H A Drectangular-tiling.ll33 ; TWO-PLUS-REGISTER: // 1st level tiling - Tiles
34 ; TWO-PLUS-REGISTER: for (int c0 = 0; c0 <= 3; c0 += 1)
35 ; TWO-PLUS-REGISTER: for (int c1 = 0; c1 <= 31; c1 += 1)
36 ; TWO-PLUS-REGISTER: // 1st level tiling - Points
37 ; TWO-PLUS-REGISTER: // 2nd level tiling - Tiles
38 ; TWO-PLUS-REGISTER: for (int c2 = 0; c2 <= 15; c2 += 1)
40 ; TWO-PLUS-REGISTER: // 2nd level tiling - Points
41 ; TWO-PLUS-REGISTER: // Register tiling - Tiles
45 ; TWO-PLUS-REGISTER: {
50 ; TWO-PLUS-REGISTER: }
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2011-02-04-AntidepMultidef.ll26 ; CHECK-NOT: [[REGISTER]],
29 ; CHECK-NOT: [[REGISTER]],
40 ; CHECK-NOT: [[REGISTER]],
43 ; CHECK-NOT: [[REGISTER]],
54 ; CHECK-NOT: [[REGISTER]],
57 ; CHECK-NOT: [[REGISTER]],
68 ; CHECK-NOT: [[REGISTER]],
71 ; CHECK-NOT: [[REGISTER]],
79 ; CHECK-NOT: [[REGISTER]],
82 ; CHECK-NOT: [[REGISTER]],
[all …]
H A Dreadonly-aliases.ll15 ; CHECK: movw [[REGISTER:r[0-9]+]], :lower16:b
16 ; CHECK: movt [[REGISTER]], :upper16:b
/llvm-project-15.0.7/llvm/test/CodeGen/Lanai/
H A Dcodemodel.ll16 ; CHECK: mov hi(data), %r[[REGISTER:[0-9]+]]
17 ; CHECK: or %r[[REGISTER]], lo(data), %r[[REGISTER]]
18 ; CHECK: ld 0[%r[[REGISTER]]], %rv
26 ; CHECK-SMALL: mov data, %r[[REGISTER:[0-9]+]]
27 ; CHECK-SMALL: ld 40[%r[[REGISTER]]], %rv
29 ; CHECK: mov hi(data), %r[[REGISTER:[0-9]+]]
30 ; CHECK: or %r[[REGISTER]], lo(data), %r[[REGISTER]]
31 ; CHECK: ld 40[%r[[REGISTER]]], %rv
42 ; CHECK-SMALL: or %r[[REGISTER]], lo(y), %r[[REGISTER]]
44 ; CHECK: mov hi(y), %r[[REGISTER:[0-9]+]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dfp-const-02.ll8 ; CHECK: lzer [[REGISTER:%f[0-5]+]]
9 ; CHECK: lcdfr %f0, [[REGISTER]]
17 ; CHECK: lzdr [[REGISTER:%f[0-5]+]]
18 ; CHECK: lcdfr %f0, [[REGISTER]]
26 ; CHECK: lzxr [[REGISTER:%f[0-5]+]]
27 ; CHECK: lcxbr %f0, [[REGISTER]]
H A Dfp-conv-06.ll9 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
10 ; CHECK: cegbr %f0, [[REGISTER]]
19 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
20 ; CHECK: cdgbr %f0, [[REGISTER]]
29 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
30 ; CHECK: cxgbr %f0, [[REGISTER]]
H A Dfp-strict-conv-06.ll13 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
14 ; CHECK: cegbr %f0, [[REGISTER]]
25 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
26 ; CHECK: cdgbr %f0, [[REGISTER]]
37 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
38 ; CHECK: cxgbr %f0, [[REGISTER]]
H A Dargs-05.ll30 ; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2
31 ; CHECK: stg [[REGISTER]], 0(%r3)
41 ; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2
42 ; CHECK: stg [[REGISTER]], 0(%r3)
H A Dfp-const-09.ll9 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
10 ; CHECK: ld %f0, 0([[REGISTER]])
11 ; CHECK: ld %f2, 8([[REGISTER]])
H A Dframe-14.ll235 ; CHECK-NOFP: llilh [[REGISTER]], 8
236 ; CHECK-NOFP: la [[REGISTER]], 0([[REGISTER]],%r15)
237 ; CHECK-NOFP: mvi 0([[REGISTER]]), 42
238 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
243 ; CHECK-FP: llilh [[REGISTER]], 8
244 ; CHECK-FP: la [[REGISTER]], 0([[REGISTER]],%r11)
245 ; CHECK-FP: mvi 0([[REGISTER]]), 42
246 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
275 ; CHECK-NOFP: llilh [[REGISTER]], 8
276 ; CHECK-NOFP: la [[REGISTER]], 0([[REGISTER]],%r15)
[all …]
H A Dfp-const-08.ll10 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
11 ; CHECK: ld %f0, 0([[REGISTER]])
12 ; CHECK: ld %f2, 8([[REGISTER]])
H A Dframe-16.ll225 ; CHECK-NOFP: llilh [[REGISTER]], 8
226 ; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
227 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
232 ; CHECK-FP: llilh [[REGISTER]], 8
233 ; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
234 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
261 ; CHECK-NOFP: llilh [[REGISTER]], 8
262 ; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
270 ; CHECK-FP: llilh [[REGISTER]], 8
271 ; CHECK-FP: stc %r3, 8([[REGISTER]],%r11)
[all …]
H A Dframe-13.ll213 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
214 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
215 ; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
216 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
220 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
221 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
222 ; CHECK-FP: mvhi 0([[REGISTER]]), 42
223 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
252 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
253 ; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
[all …]
H A Dfp-const-03.ll8 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
9 ; CHECK: le %f0, 0([[REGISTER]])
H A Dfp-const-06.ll8 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
9 ; CHECK: ld %f0, 0([[REGISTER]])
H A Dfp-const-04.ll9 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
10 ; CHECK: ld %f0, 0([[REGISTER]])
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/Windows/
H A Dpowi.ll13 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
14 ; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
25 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
26 ; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
38 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
39 ; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
52 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
53 ; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/SkylakeClient/
H A Dbottleneck-analysis.s56 # CHECK-NEXT: +----> 0. vmovups (%rsi,%rax,2), %xmm0 ## REGISTER dependency: %rax
59 # CHECK-NEXT: +----> 3. vpermilps $170, %xmm0, %xmm6 ## REGISTER dependency: %x…
62 # CHECK-NEXT: +----> 6. vfmadd231ps %xmm9, %xmm6, %xmm8 ## REGISTER dependency: %xmm6
63 # CHECK-NEXT: +----> 7. vfmadd213ps %xmm8, %xmm10, %xmm5 ## REGISTER dependency: %xmm8
64 # CHECK-NEXT: +----> 8. vfmadd213ps %xmm5, %xmm11, %xmm0 ## REGISTER dependency: %xmm5
65 # CHECK-NEXT: +----> 9. vfmadd213ps %xmm0, %xmm12, %xmm4 ## REGISTER dependency: %xmm0
66 # CHECK-NEXT: +----> 10. vfmadd213ps %xmm4, %xmm13, %xmm1 ## REGISTER dependency: %xmm4
68 # CHECK-NEXT: +----> 12. vfmadd213ps %xmm1, %xmm14, %xmm2 ## REGISTER dependency: %xmm1
70 # CHECK-NEXT: +----> 14. vfmadd213ps %xmm2, %xmm15, %xmm3 ## REGISTER dependency: %xmm2
71 # CHECK-NEXT: +----> 15. vpermilps $170, %xmm3, %xmm0 ## REGISTER dependency: %x…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dsetltk.ll18 ; 16: slti $[[REGISTER:[0-9]+]], 10
19 ; MMR6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
20 ; 16: move $[[REGISTER]], $24
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A D2012-10-12-bitcast.ll17 ; CHECK: addi [[REGISTER:[0-9]+]], 1, -16
18 ; CHECK: stvx 2, 0, [[REGISTER]]
22 ; CHECK-VSX: addi [[REGISTER:[0-9]+]], 1, -16
23 ; CHECK-VSX: stxvd2x 34, 0, [[REGISTER]]
/llvm-project-15.0.7/llvm/test/CodeGen/XCore/
H A Dbigstructret.ll26 ; CHECK: ldc [[REGISTER:r[0-9]+]], 5
27 ; CHECK-NEXT: stw [[REGISTER]], sp[2]
40 ; CHECK: ldc [[REGISTER:r[0-9]+]], 0
41 ; CHECK: stw [[REGISTER]], sp[1]
H A D2011-08-01-DynamicAllocBug.ll17 ; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1]
18 ; CHECK: set sp, [[REGISTER]]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BtVer2/
H A Dbottleneck-hints-1.s33 # CHECK-NEXT: +----> 0. addl %eax, %ebx ## REGISTER dependency: %eax
34 # CHECK-NEXT: +----> 1. addl %ebx, %ecx ## REGISTER dependency: %ebx
35 # CHECK-NEXT: +----> 2. addl %ecx, %edx ## REGISTER dependency: %ecx
36 # CHECK-NEXT: +----> 3. addl %edx, %eax ## REGISTER dependency: %edx
40 # CHECK-NEXT: +----> 0. addl %eax, %ebx ## REGISTER dependency: %eax
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpreallocated.ll40 ; CHECK: leal (%esp), [[REGISTER:%[a-z]+]]
45 ; CHECK-DAG: movl $13, ([[REGISTER]])
46 ; CHECK-DAG: movl $42, 4([[REGISTER]])
58 ; CHECK: leal (%esp), [[REGISTER:%[a-z]+]]
60 ; CHECK: pushl [[REGISTER]]
89 ; CHECK: leal (%esp), [[REGISTER:%[a-z]+]]
91 ; CHECK: pushl [[REGISTER]]
H A Dcmpxchg8b_alloca_regalloc_handling.ll17 ; CHECK: leal {{\(%e..,%e..,.*\)}}, [[REGISTER:%e.i]]
22 ; CHECK-NEXT: lock cmpxchg8b ([[REGISTER]])
34 ; CHECK-NOT: leal {{\(%e.*\)}}, [[REGISTER:%e.i]]
35 ; CHECK: lock cmpxchg8b ([[REGISTER]])

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