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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
38 let RA = 0;
45 bits<5> RA;
50 let Inst{11-15} = RA;
59 bits<5> RA;
65 let Inst{11-15} = RA;
79 let RA = 0;
86 bits<5> RA;
93 let Inst{11-15} = RA;
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H A DPPCMacroFusion.cpp104 const MachineOperand &RA = SecondMI.getOperand(1); in checkOpConstraints() local
105 if (!RA.isReg()) in checkOpConstraints()
108 return Register::isVirtualRegister(RA.getReg()) || in checkOpConstraints()
109 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
206 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
208 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
210 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
217 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
219 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
221 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
H A DPPCInstrHTM.td106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
110 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
116 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
121 def : Pat<(int_ppc_treclaim i32:$RA),
122 (TRECLAIM $RA)>;
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcmpxchg-clobber-flags.ll29 ; 32-GOOD-RA-NEXT: pushl %ebx
30 ; 32-GOOD-RA-NEXT: pushl %esi
31 ; 32-GOOD-RA-NEXT: pushl %eax
38 ; 32-GOOD-RA-NEXT: setne %bl
54 ; 32-GOOD-RA-NEXT: popl %esi
55 ; 32-GOOD-RA-NEXT: popl %ebx
56 ; 32-GOOD-RA-NEXT: retl
69 ; 32-FAST-RA-NEXT: setne %bl
87 ; 32-FAST-RA-NEXT: retl
231 ; 32-GOOD-RA-NEXT: retl
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H A Dfold-call-3.ll5 … RUN: llc < %s -mtriple=x86_64-apple-darwin -pre-RA-sched=linearize | FileCheck %s --check-prefix=…
45 ; pre-RA-NEXT: pushq %rbp
46 ; pre-RA-NEXT: pushq %rbx
47 ; pre-RA-NEXT: subq $24, %rsp
49 ; pre-RA-NEXT: je LBB0_3
55 ; pre-RA-NEXT: LBB0_2: ## %bb
61 ; pre-RA-NEXT: incl %ebp
65 ; pre-RA-NEXT: jb LBB0_2
68 ; pre-RA-NEXT: popq %rbx
69 ; pre-RA-NEXT: popq %rbp
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H A Dvirtual-registers-cleared-in-machine-functions-liveins.ll1 …e=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
2 …riple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
13 ; PRE-RA: liveins:
14 ; PRE-RA-NEXT: - { reg: '$edi', virtual-reg: '%0' }
15 ; PRE-RA-NEXT: - { reg: '$esi', virtual-reg: '%1' }
17 ; POST-RA: liveins:
18 ; POST-RA-NEXT: - { reg: '$edi', virtual-reg: '' }
19 ; POST-RA-NEXT: - { reg: '$esi', virtual-reg: '' }
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsplitkit-copy-bundle.mir13 ; RA: bb.0:
15 ; RA-NEXT: {{ $}}
21 ; RA-NEXT: {{ $}}
22 ; RA-NEXT: bb.1:
24 ; RA-NEXT: {{ $}}
84 ; RA-NEXT: {{ $}}
85 ; RA-NEXT: bb.2:
87 ; RA-NEXT: {{ $}}
90 ; RA-NEXT: S_BRANCH %bb.2
273 ; RA-NEXT: }
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H A Dsendmsg-m0-hazard.mir1 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
2 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | F…
3 # RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
4 # RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - |…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/PowerPC/
H A Dppc64-encoding-ISA31-invalid.txt4 # paddi 1, 2, 8589934591, 1. However, RA is not zero with R=1
8 # plbz 1, 8589934591(2), 1. However, RA is not zero with R=1
12 # plfd 1, 8589934591(2), 1. However, RA is not zero with R=1
16 # plfs 1, 8589934591(2), 1. However, RA is not zero with R=1
20 # plha 1, 8589934591(2), 1. However, RA is not zero with R=1
24 # plhz 1, 8589934591(2), 1. However, RA is not zero with R=1
28 # plwz 1, 8589934591(2), 1. However, RA is not zero with R=1
32 # pstb 1, 8589934591(2), 1. However, RA is not zero with R=1
36 # pstfd 1, 8589934591(2), 1. However, RA is not zero with R=1
44 # psth 1, 8589934591(2), 1. However, RA is not zero with R=1
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DRDFDeadCode.cpp89 if (!LiveNodes.count(RA.Id)) in scanInstr()
90 WorkQ.push_back(RA.Id); in scanInstr()
135 auto RA = DFG.addr<RefNode*>(N); in collect() local
136 if (DFG.IsDef(RA)) in collect()
137 processDef(RA, WorkQ); in collect()
139 processUse(RA, WorkQ); in collect()
161 DeadNodes.insert(RA.Id); in collect()
223 if (DFG.IsUse(RA)) in erase()
224 DFG.unlinkUse(RA, true); in erase()
225 else if (DFG.IsDef(RA)) in erase()
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H A DHexagonRDFOpt.cpp166 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) { in run()
167 R2I.insert(std::make_pair(RA.Id, SA.Id)); in run()
168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
201 for (NodeAddr<RefNode*> RA : Refs) in removeOperand()
202 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); in removeOperand()
206 for (NodeAddr<RefNode*> RA : Refs) { in removeOperand()
207 unsigned N = OpMap[RA.Id]; in removeOperand()
209 RA.Addr->setRegRef(&MI->getOperand(N), DFG); in removeOperand()
211 RA.Addr->setRegRef(&MI->getOperand(N-1), DFG); in removeOperand()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegAllocEvictionAdvisor.cpp78 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
79 return std::make_unique<DefaultEvictionAdvisor>(MF, RA); in getAdvisor()
126 const RAGreedy &RA) in RegAllocEvictionAdvisor() argument
127 : MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()), in RegAllocEvictionAdvisor()
128 LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()), in RegAllocEvictionAdvisor()
130 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
151 bool CanSplit = RA.getExtraInfo().getStage(B) < RS_Spill; in shouldEvict()
201 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in canEvictInterferenceBasedOnCost()
223 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in canEvictInterferenceBasedOnCost()
238 unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); in canEvictInterferenceBasedOnCost()
H A DRDFGraph.cpp794 RA.Addr->setSibling(0); in cloneNode()
1116 NodeId Start = RA.Id; in getRelatedRefs()
1118 Refs.push_back(RA); in getRelatedRefs()
1119 RA = getNextRelated(IA, RA); in getRelatedRefs()
1120 } while (RA.Id != 0 && RA.Id != Start); in getRelatedRefs()
1181 NodeId Start = RA.Id; in locateNextRef()
1188 RA = NA; in locateNextRef()
1535 if (RA.Addr->isDef()) in removeUnusedPhis()
1631 return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering); in linkBlockRefs()
1634 return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering); in linkBlockRefs()
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H A DRegAllocEvictionAdvisor.h123 RegAllocEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA);
139 const RAGreedy &RA; variable
178 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
205 DefaultEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA) in DefaultEvictionAdvisor() argument
206 : RegAllocEvictionAdvisor(MF, RA) {} in DefaultEvictionAdvisor()
/llvm-project-15.0.7/clang/test/Layout/
H A Dms-x86-alias-avoidance-padding.cpp253 struct RA {}; struct
258 struct RX0 : RB, RA {};
259 struct RX1 : RA, RB {};
260 struct RX2 : RA { char a; };
261 struct RX3 : RA { RB a; };
262 struct RX4 { RA a; char b; };
263 struct RX5 { RA a; RB b; };
265 struct RX7 : virtual RW { RA a; };
266 struct RX8 : RA, virtual RW {};
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DReachingDefOrUse.h36 ReachingDefOrUse(const RegAnalysis &RA, BinaryFunction &BF,
40 RA(RA), TrackingReg(TrackingReg) {}
47 RA.getInstClobberList(**I, BV); in isReachedBy()
64 const RegAnalysis &RA;
99 RA.getInstClobberList(*X, XClobbers); in doesXKillsY()
103 RA.getInstClobberList(*Y, YClobbers); in doesXKillsY()
135 RA.getInstClobberList(Point, Regs); in computeNext()
137 RA.getInstUsedRegsList(Point, Regs, false); in computeNext()
H A DLivenessAnalysis.h33 LivenessAnalysis(const RegAnalysis &RA, BinaryFunction &BF, in LivenessAnalysis() argument
35 : Parent(BF, AllocId), RA(RA), in LivenessAnalysis()
67 const RegAnalysis &RA;
105 RA.getInstClobberList(Point, Written); in computeNext()
110 if (RA.isConservative(Written)) { in computeNext()
132 RA.getInstUsedRegsList(Point, Used, /*GetClobbers*/ true); in computeNext()
133 if (RA.isConservative(Used)) { in computeNext()
H A DDataflowInfoManager.h30 const RegAnalysis *RA; variable
52 DataflowInfoManager(BinaryFunction &BF, const RegAnalysis *RA,
55 : RA(RA), FA(FA), BC(BF.getBinaryContext()), BF(BF), in RA() argument
/llvm-project-15.0.7/bolt/lib/Passes/
H A DDataflowInfoManager.cpp21 assert(RA && "RegAnalysis required"); in getReachingDefs()
22 RD.reset(new ReachingDefOrUse<true>(*RA, BF, None, AllocatorId)); in getReachingDefs()
32 assert(RA && "RegAnalysis required"); in getReachingUses()
33 RU.reset(new ReachingDefOrUse<false>(*RA, BF, None, AllocatorId)); in getReachingUses()
43 assert(RA && "RegAnalysis required"); in getLivenessAnalysis()
44 LA.reset(new LivenessAnalysis(*RA, BF, AllocatorId)); in getLivenessAnalysis()
H A DStackAvailableExpressions.cpp23 StackAvailableExpressions::StackAvailableExpressions(const RegAnalysis &RA, in StackAvailableExpressions() argument
26 : InstrsDataflowAnalysis(BF), RA(RA), FA(FA) {} in StackAvailableExpressions()
97 RA.getInstClobberList(*X, XClobbers); in doesXKillsY()
104 RA.getInstClobberList(*Y, YClobbers); in doesXKillsY()
H A DStokeInfo.cpp88 RegAnalysis &RA, StokeFuncInfo &FuncInfo) { in checkFunction() argument
133 BitVector LiveOutBV = RA.getFunctionClobberList(&BF); in checkFunction()
158 RegAnalysis RA(BC, &BC.getBinaryFunctions(), &CG); in runOnFunctions() local
176 DataflowInfoManager DInfo(BF.second, &RA, nullptr); in runOnFunctions()
178 if (checkFunction(BF.second, DInfo, RA, FuncInfo)) in runOnFunctions()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h118 bool alias(RegisterRef RA, RegisterRef RB) const { in alias()
119 if (!isRegMaskId(RA.Reg)) in alias()
120 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias()
121 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias()
163 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
182 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
184 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
/llvm-project-15.0.7/llvm/lib/Object/
H A DRelocationResolver.cpp453 int64_t RA = Addend; in resolveRISCV() local
459 return (S + RA) & 0xFFFFFFFF; in resolveRISCV()
463 return S + RA; in resolveRISCV()
469 return (A + (S + RA)) & 0xFF; in resolveRISCV()
471 return (A - (S + RA)) & 0xFF; in resolveRISCV()
473 return (A + (S + RA)) & 0xFFFF; in resolveRISCV()
475 return (A - (S + RA)) & 0xFFFF; in resolveRISCV()
477 return (A + (S + RA)) & 0xFFFFFFFF; in resolveRISCV()
479 return (A - (S + RA)) & 0xFFFFFFFF; in resolveRISCV()
481 return (A + (S + RA)); in resolveRISCV()
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/llvm-project-15.0.7/llvm/include/llvm/Transforms/IPO/
H A DDeadArgumentElimination.h130 bool isLive(const RetOrArg &RA);
131 void markValue(const RetOrArg &RA, Liveness L,
133 void markLive(const RetOrArg &RA);
135 void propagateLiveness(const RetOrArg &RA);
/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp651 markLive(RA); in markValue()
654 assert(!isLive(RA) && "Use is already live!"); in markValue()
658 markLive(RA); in markValue()
663 Uses.emplace(MaybeLiveUse, RA); in markValue()
688 if (isLive(RA)) in markLive()
691 LiveValues.insert(RA); in markLive()
694 << RA.getDescription() << " live\n"); in markLive()
695 propagateLiveness(RA); in markLive()
699 return LiveFunctions.count(RA.F) || LiveValues.count(RA); in isLive()
708 UseMap::iterator Begin = Uses.lower_bound(RA); in propagateLiveness()
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