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/llvm-project-15.0.7/lldb/unittests/Utility/
H A DRegisterValueTest.cpp16 RegisterValue R8(uint8_t(47)); in TEST() local
17 EXPECT_EQ(47u, R8.GetAsUInt8()); in TEST()
18 R8 = uint8_t(42); in TEST()
19 EXPECT_EQ(42u, R8.GetAsUInt8()); in TEST()
20 EXPECT_EQ(42u, R8.GetAsUInt16()); in TEST()
21 EXPECT_EQ(42u, R8.GetAsUInt32()); in TEST()
22 EXPECT_EQ(42u, R8.GetAsUInt64()); in TEST()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrInfo.td35 def R8 : RegisterClass;
87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
89 [(set R8:$dst, R8:$src)]>;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td29 // A SwiftError is passed in R8.
30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
55 // A SwiftError is returned in R8.
56 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
174 // A SwiftError is passed in R8.
192 // A SwiftError is returned in R8.
219 // A SwiftError is passed in R8.
242 // A SwiftError is returned in R8.
278 // R8 is used to pass swifterror, remove it from CSR.
296 // R8 is used to pass swifterror, remove it from CSR.
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H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
81 case R8: case R9: case R10: case R12: in isSplitFPArea1Register()
H A DThumb1InstrInfo.cpp29 .addReg(ARM::R8) in getNop()
30 .addReg(ARM::R8) in getNop()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcttz-v.ll17 ; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]]
19 ; MIPS32-DAG: subu $3, $[[R4]], $[[R8]]
30 ; MIPS64-DAG: dext $[[R8:[0-9]+]], $[[R5]], 0, 32
37 ; MIPS64-DAG: or $2, $[[R8]], $[[R14]]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td63 def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td34 def RV : LanaiReg< 8, "rv", [R8]>, DwarfRegAlias<R8>;
51 R8, RV, // return value
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S59 #define exp R8
158 #define exp R8
257 #define mantbl_ R8
262 #define c8001 R8
H A Dfastmath2_dlib_asm.S65 #define exp R8
166 #define exp R8
268 #define exp R8
H A Dfastmath_dlib_asm.S67 #define exp R8
202 #define exp R8
330 #define exp R8
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp42 return TFI->hasFP(MF) ? CSKY::R8 : CSKY::R14; in getFrameRegister()
56 markSuperRegs(Reserved, CSKY::R8); // fp in getReservedRegs()
60 markSuperRegs(Reserved, CSKY::R8 + i); // R8 - R13 in getReservedRegs()
H A DCSKYCallingConv.td13 def CSR_I32 : CalleeSavedRegs<(add R8, R15, (sequence "R%u", 4, 7),
21 def CSR_GPR_ISR : CalleeSavedRegs<(add R8, R15,
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dswp-art-deps-rec.ll46 …%R8.0469.us.ur = phi i32 [ %sub34.us.ur, %L57.us.ur ], [ undef, %entry ], [ undef, %for.cond22.for…
53 %5 = inttoptr i32 %R8.0469.us.ur to i16*
56 %sub31.us.ur = add i32 %R8.0469.us.ur, -8
63 %sub34.us.ur = add i32 %R8.0469.us.ur, -16
/llvm-project-15.0.7/lldb/source/Plugins/Process/Windows/Common/x64/
H A DRegisterContextWindows_x64.cpp360 GPR_CASE(64, lldb_r8_x86_64, m_context.R8); in ReadRegister()
380 GPR_CASE(32, lldb_r8d_x86_64, static_cast<uint32_t>(m_context.R8)); in ReadRegister()
396 GPR_CASE(16, lldb_r8w_x86_64, static_cast<uint16_t>(m_context.R8)); in ReadRegister()
416 GPR_CASE(8, lldb_r8l_x86_64, static_cast<uint8_t>(m_context.R8)); in ReadRegister()
522 m_context.R8 = reg_value.GetAsUInt64(); in WriteRegister()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFFrameLowering.cpp37 SavedRegs.reset(BPF::R8); in determineCalleeSaves()
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dreg-types.ll55 ; CHECK: mov.u64 [[R8:%rd[0-9]]], 8;
56 ; CHECK-NEXT: st.u64 {{.*}}, [[R8]]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td44 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
91 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
122 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test198 - 'ROL64ri R8 R8 i_0x1'
215 - 'R8=0x0'
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h61 case Lanai::R8: in getLanaiRegisterNumbering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.td71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
78 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
410 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
439 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
548 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
610 RDI, RSI, RDX, RCX, R8, R9,
672 [RCX , RDX , R8 , R9 ]>>,
688 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
731 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
1149 R8, R9, R10, R11)>;
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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dbuild-attributes.ll1301 ; CORTEX-R8: .cpu cortex-r8
1302 ; CORTEX-R8: .eabi_attribute 6, 10
1303 ; CORTEX-R8: .eabi_attribute 7, 82
1304 ; CORTEX-R8: .eabi_attribute 8, 1
1305 ; CORTEX-R8: .eabi_attribute 9, 2
1306 ; CORTEX-R8: .fpu vfpv3-d16-fp16
1307 ; CORTEX-R8: .eabi_attribute 36, 1
1308 ; CORTEX-R8: .eabi_attribute 42, 1
1309 ; CORTEX-R8: .eabi_attribute 44, 2
1313 ; CORTEX-R8: .eabi_attribute 20, 1
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