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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dfmax-fmin.ll6 ; R32-LABEL: maxnum_f32:
7 ; R32: # %bb.0:
13 ; R32-NEXT: ret
29 ; R32: # %bb.0:
38 ; R32-NEXT: # %bb.1:
40 ; R32-NEXT: .LBB1_2:
46 ; R32-NEXT: ret
79 ; R32-NEXT: ret
131 ; R32-NEXT: ret
164 ; R32-NEXT: ret
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/gdb-remote/
H A DGDBRemoteRegisterFallback.cpp21 #define R32(name) REG(name, 4) macro
32 R64(x28), R64(x29), R64(x30), R64(sp), R64(pc), R32(cpsr), in GetRegisters_aarch64()
43 R32(eax), R32(ecx), R32(edx), R32(ebx), R32(esp), R32(ebp), in GetRegisters_x86()
44 R32(esi), R32(edi), R32(eip), R32(eflags), R32(cs), R32(ss), in GetRegisters_x86()
45 R32(ds), R32(es), R32(fs), R32(gs), in GetRegisters_x86()
58 R64(r12), R64(r13), R64(r14), R64(r15), R64(rip), R32(eflags), in GetRegisters_x86_64()
59 R32(cs), R32(ss), R32(ds), R32(es), R32(fs), R32(gs), in GetRegisters_x86_64()
65 #undef R32
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTree.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
H A DTreeNames.td11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
H A DTargetInstrInfo.td37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-legalize-divmod.mir143 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
193 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
245 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
295 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
427 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
430 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
480 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
483 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
535 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
538 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
[all …]
H A Darm-legalize-bitcounts.mir119 ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
122 ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[R32]], [[BITDIFF]]
163 ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
166 ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[R32]], [[BITDIFF]]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll59 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
75 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
92 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
108 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
124 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
141 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
157 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
738 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
756 ; XCHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
951 ; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]]
[all …]
H A Dparam-load-store.ll181 ; CHECK: ld.param.b32 [[R32:%r[0-9]+]], [retval0+0];
182 ; CHECK: and.b32 [[R:%r[0-9]+]], [[R32]], 255;
201 ; CHECK: ld.param.b32 [[R32:%r[0-9]+]], [retval0+0];
203 ; CHECK: cvt.u16.u32 [[R16:%rs[0-9]+]], [[R32]];
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2006-05-08-CoalesceSubRegClass.ll2 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td53 // Define extended core registers R32..R63
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics-gfx8.ll47 ; CHECK-NEXT: [[R32:%.*]] = fpext half [[R:%.*]] to float
48 …cn.image.sample.3d.v4f32.f32(i32 15, float [[S32]], float [[T32]], float [[R32]], <8 x i32> [[RSRC…
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dfunnel-shift.ll32 ; CHECK: r[[R32:[0-9]+]] = sub(#64,r4)
33 ; CHECK: r[[R30]]:[[R31]] |= lsr(r3:2,r[[R32]])
H A Drotate.ll42 ; CHECK: r[[R32:[0-9]+]]:[[R33:[0-9]+]] = lsr(r[[R30]]:[[R31]],r1)
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp1397 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass; in generateInserts() local
1398 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert) in generateInserts()
1403 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) { in generateInserts()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dalternate-int.ll451 ; AVX2-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 un…
452 ; AVX2-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
468 ; AVX512-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 …
469 ; AVX512-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
H A Dalternate-int-inseltpoison.ll451 ; AVX2-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 un…
452 ; AVX2-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
468 ; AVX512-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 …
469 ; AVX512-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
H A Darith-add-saddo.ll835 ; CHECK-NEXT: [[R32:%.*]] = extractvalue { i8, i1 } [[C32]], 0
899 ; CHECK-NEXT: store i8 [[R32]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @c8, i32 0, i6…
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td86 def R32 : CSKYReg<32, "r32", ["r32"]>, DwarfRegNum<[32]>;
/llvm-project-15.0.7/llvm/unittests/IR/
H A DConstantRangeTest.cpp2438 ConstantRange R32(APInt(8, 32)); in TEST_F() local
2439 EXPECT_TRUE(R16_32.binaryAnd(R32).getSingleElement()->isZero()); in TEST_F()
2440 EXPECT_TRUE(R32.binaryAnd(R16_32).getSingleElement()->isZero()); in TEST_F()
2472 ConstantRange R32(APInt(8, 32)); in TEST_F() local
2474 EXPECT_EQ(R16_32.binaryOr(R32), R48_64); in TEST_F()
2475 EXPECT_EQ(R32.binaryOr(R16_32), R48_64); in TEST_F()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dshuff-combos-64b.ll46 ; CHECK-DAG: [[R32:r[0-9]+]] = #5
49 ; CHECK: v[[H32:[0-9]+]]:[[L32:[0-9]+]] = vdeal(v[[H31]],v[[L31]],[[R32]])
H A Dshuff-combos-128b.ll53 ; CHECK-DAG: [[R32:r[0-9]+]] = #34
57 ; CHECK: v[[H32:[0-9]+]]:[[L32:[0-9]+]] = vshuff(v[[H31]],v[[L31]],[[R32]])
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td755 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td713 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LD(R|R32|GR)$")>;
H A DSystemZScheduleZEC12.td751 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LD(R|R32|GR)$")>;

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