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/llvm-project-15.0.7/compiler-rt/lib/builtins/avr/
H A Ddivmodhi4.S49 ret ; Return quotient via R23:R22 and remainder via R25:R24.
57 ret ; Return quotient via R23:R22 and remainder via R25:r24.
H A Dudivmodhi4.S46 mov r23, r25 ; The quotient is returned in R23:R22.
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td59 def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>;
84 def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>;
99 def R24R23 : AVRReg<23, "r24:r23", [R23, R24]>, DwarfRegNum<[23]>;
117 add R24, R25, R18, R19, R20, R21, R22, R23,
133 add R24, R25, R18, R19, R20, R21, R22, R23,
141 (add R23, R22, R21, R20, R19, R18, R17, R16)>;
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dalternate-calls.ll23 ; SSE-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32…
24 ; SSE-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
44 ; SLM-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32…
45 ; SLM-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
65 ; AVX-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32…
66 ; AVX-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
H A Dalternate-calls-inseltpoison.ll23 ; SSE-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32…
24 ; SSE-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
44 ; SLM-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32…
45 ; SLM-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
65 ; AVX-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32…
66 ; AVX-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dtwo-extenders.s107 {R23 = #1; memh(##0x1000) = R23.new}
H A Dnot-over.s30 R23:22 = MEMD(R0+#24)
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h95 case Lanai::R23: in getLanaiRegisterNumbering()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp122 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
131 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
H A DHexagonFrameLowering.h96 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 }, in getCalleeSavedSpillSlots()
H A DHexagonRegisterInfo.td148 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
539 (add R23, R22, R21, R20, R19, R18, R17, R16,
643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYInstPrinter.cpp117 if (Reg == CSKY::R23) in printOperand()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td66 def R23 : LoongArchReg<23, "r23", ["s0"]>, DwarfRegNum<[23]>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td272 R21, R22, R23, R24, R25, R26, R27,
288 R21, R22, R23, R24, R25, R26, R27, R28,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td75 def R23 : CSKYReg<23, "r23", ["t7"]>, DwarfRegNum<[23]>;
H A DCSKYFrameLowering.cpp389 CSKY::R21, CSKY::R22, CSKY::R23, in determineCalleeSaves()
/llvm-project-15.0.7/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp128 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp63 AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp561 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, in DecodeIntRegsRegisterClass()
576 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in DecodeGeneralSubRegsRegisterClass()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp305 case R23: in getDuplexRegisterNumbering()
658 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23)); in isIntRegForSubInst()
H A DHexagonMCChecker.cpp749 Register = Hexagon::R23; in compoundRegisterMap()
H A DHexagonMCDuplexInfo.cpp683 case Hexagon::R23: in addOps()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp69 CSKY::R21, CSKY::R22, CSKY::R23, CSKY::R24, CSKY::R25, CSKY::R26, CSKY::R27,
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dparam-load-store.ll443 ; CHECK: ld.param.v2.u32 {[[R01:%r[0-9]+]], [[R23:%r[0-9]+]]}, [test_v4f16_param_0];
445 ; CHECK-DAG: mov.b32 [[HH23:%hh[0-9]+]], [[R23]];
484 ; CHECK: ld.param.v4.u32 {[[R01:%r[0-9]+]], [[R23:%r[0-9]+]], [[R45:%r[0-9]+]], [[R67:%r[0-9]+…
486 ; CHECK-DAG: mov.b32 [[HH23:%hh[0-9]+]], [[R23]];

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