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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dfmul-v67.ll26 ; CHECK-DAG: [[R20:(r[0-9]+:[0-9]+)]] = dfmpyfix(r1:0,r3:2)
28 ; CHECK: [[R22:(r[0-9]+:[0-9]+)]] = dfmpyll([[R20]],[[R21]])
29 ; CHECK: [[R22]] += dfmpylh([[R20]],[[R21]])
30 ; CHECK: [[R22]] += dfmpylh([[R21]],[[R20]])
31 ; CHECK: [[R22]] += dfmpyhh([[R20]],[[R21]])
H A Drotate-multi.ll38 ; CHECK: r[[R20:[0-9]+]] = asl(r0,#11)
41 ; CHECK: r[[R20]] |= asl(r1,#19)
42 ; CHECK: r[[R20]] |= or(r[[R21]],r[[R22]])
H A Dbit-cmp0.mir50 # CHECK: %[[R20:[0-9]+]]:intregs = A2_tfrsi 0
51 # CHECK: $r0 = COPY %[[R20]]
H A Drdf-copy-undef.ll4 ; After a copy R20 = R29, RDF copy propagation attempted to replace R20 with
H A Dfunnel-shift.ll22 ; CHECK: r[[R20:[0-9]+]]:[[R21:[0-9]+]] = asl(r1:0,#17)
23 ; CHECK: r[[R20]]:[[R21]] |= lsr(r3:2,#47)
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dzext.ll12 ; zext R25:R24, R20
13 ; mov R24, R20
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td56 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>;
85 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
101 def R20R19 : AVRReg<19, "r20:r19", [R19, R20]>, DwarfRegNum<[19]>;
117 add R24, R25, R18, R19, R20, R21, R22, R23,
133 add R24, R25, R18, R19, R20, R21, R22, R23,
141 (add R23, R22, R21, R20, R19, R18, R17, R16)>;
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h89 case Lanai::R20: in getLanaiRegisterNumbering()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp122 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
131 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
H A DHexagonFrameLowering.h95 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
H A DHexagonRegisterInfo.td147 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
539 (add R23, R22, R21, R20, R19, R18, R17, R16,
643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dtwo-extenders.s129 memh(##0x1000) = R20
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td63 def R20 : LoongArchReg<20, "r20", ["t8"]>, DwarfRegNum<[20]>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td271 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
287 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td72 def R20 : CSKYReg<20, "r20", ["t4"]>, DwarfRegNum<[20]>;
H A DCSKYFrameLowering.cpp388 static const MCPhysReg CSHRegs[] = {CSKY::R18, CSKY::R19, CSKY::R20, in determineCalleeSaves()
/llvm-project-15.0.7/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp62 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
/llvm-project-15.0.7/llvm/unittests/IR/
H A DConstantRangeTest.cpp2432 ConstantRange R20(APInt(8, 20)); in TEST_F() local
2434 EXPECT_EQ(*R16.binaryAnd(R20).getSingleElement(), APInt(8, 16 & 20)); in TEST_F()
2464 ConstantRange R20(APInt(8, 20)); in TEST_F() local
2466 EXPECT_EQ(*R16.binaryOr(R20).getSingleElement(), APInt(8, 16 | 20)); in TEST_F()
2502 ConstantRange R20(APInt(8, 20)); in TEST_F() local
2504 EXPECT_EQ(*R16.binaryXor(R20).getSingleElement(), APInt(8, 16 ^ 20)); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp561 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, in DecodeIntRegsRegisterClass()
576 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in DecodeGeneralSubRegsRegisterClass()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp68 CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp758 Register = Hexagon::R20; in compoundRegisterMap()
H A DHexagonMCDuplexInfo.cpp680 case Hexagon::R20: in addOps()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dshuff-combos-64b.ll31 ; CHECK-DAG: [[R20:r[0-9]+]] = #5
33 ; CHECK: v[[H20:[0-9]+]]:[[L20:[0-9]+]] = vdeal(v1,v0,[[R20]])

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