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/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S266 #define min R13:12
267 #define minh R13
268 #define max R13:12
269 #define maxh R13
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
H A DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td68 def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcttz-v.ll35 ; MIPS64-DAG: subu $[[R13:[0-9]+]], $[[R4]], $[[R12]]
36 ; MIPS64-DAG: dsll $[[R14:[0-9]+]], $[[R13]], 32
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td49 def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>;
89 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
104 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/llvm-project-15.0.7/lldb/source/Plugins/Process/Windows/Common/x64/
H A DRegisterContextWindows_x64.cpp365 GPR_CASE(64, lldb_r13_x86_64, m_context.R13); in ReadRegister()
385 GPR_CASE(32, lldb_r13d_x86_64, static_cast<uint32_t>(m_context.R13)); in ReadRegister()
401 GPR_CASE(16, lldb_r13w_x86_64, static_cast<uint16_t>(m_context.R13)); in ReadRegister()
421 GPR_CASE(8, lldb_r13l_x86_64, static_cast<uint8_t>(m_context.R13)); in ReadRegister()
537 m_context.R13 = reg_value.GetAsUInt64(); in WriteRegister()
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Ddcfetch.s12 R13:12 = VALIGNB(R11:10,R9:8,P2)
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test203 - 'ROL64ri R13 R13 i_0x1'
220 - 'R13=0x0'
/llvm-project-15.0.7/llvm/test/CodeGen/MSP430/
H A Dcmp-return-type.ll20 ; bis r12, r13 <-- checking (R12:R13)
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dsext.ll3 ; sext R17:R16, R13
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h74 case Lanai::R13: in getLanaiRegisterNumbering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.td78 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
440 RAX, R10, R11, R13, R14, R15]>>
528 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,
611 RAX, R10, R11, R13, R14]>>
640 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,
1129 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1132 def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>;
1143 def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>;
1168 R11, R12, R13, R14, R15, RBP,
1194 R13, R14, R15,
[all …]
H A DX86RegisterInfo.td185 def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
386 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
389 // Allocate R12 and R13 last, as these require an extra byte when
431 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
437 RBX, R14, R15, R12, R13, RBP)>;
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp268 {codeview::RegisterId::R13, X86::R13}, in initLLVMToSEHAndCVRegMapping()
795 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
832 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
868 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
904 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
905 return X86::R13; in getX86SubSuperRegisterOrZero()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp70 return TT.isArch64Bit() ? PPC::X13 : PPC::R13; in getScratchMemoryRegister()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dadd.ll144 ; PRE4: addu $[[R13:[0-9]+]], $[[R1]], $[[R12]]
146 ; PRE4: addu $[[R15:[0-9]+]], $[[R13]], $[[R7]]
148 ; PRE4: sltu $[[R17:[0-9]+]], $[[R15]], $[[R13]]
149 ; PRE4: sltu $[[R18:[0-9]+]], $[[R13]], $[[R1]]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h183 ENTRY(R13) \
201 ENTRY(R13) \
/llvm-project-15.0.7/compiler-rt/lib/asan/
H A Dasan_rtl_x86_64.S140 ASAN_MEMORY_ACCESS_CALLBACKS_ADD(R13)
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-multi-reduction-outer-lowering.mlir151 // CHECK: %[[R13:.+]] = arith.addi %[[V14]], %[[R12]] : vector<6xi32>
153 // CHECK: %[[R14:.+]] = arith.addi %[[V15]], %[[R13]] : vector<6xi32>
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/vect/
H A Dsetcc-v32.ll149 ; CHECK: [[R13:r[0-9:]+]] = vsxthw(r1)
150 ; CHECK: [[P13:p[0-3]+]] = vcmpw.gt([[L13]],[[R13]])
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dghc-cc64.ll5 @base = external dso_local global i64 ; assigned to register: R13
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,

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