| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrMVE.td | 611 bits<4> Qm;
664 bits<3> Qm;
762 bits<3> Qm;
834 bits<3> Qm;
895 bits<3> Qm;
1022 bits<3> Qm;
1258 bits<3> Qm;
1410 bits<4> Qm;
1507 bits<4> Qm;
1947 bits<4> Qm;
[all …]
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| H A D | ARMInstrCDE.td | 333 iname#"${vp}\t$coproc, $Qd, $Qm, $imm", params.Cstr,
337 bits<3> Qm;
349 let Inst{3-1} = Qm{2-0};
400 iname#"${vp}\t$coproc, $Qd, $Qn, $Qm, $imm", params.Cstr,
404 bits<3> Qm;
418 let Inst{3-1} = Qm{2-0};
484 let Rm = (ins regclass:$Qm);
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| H A D | ARMInstrNEON.td | 9009 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
9011 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
9013 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
9015 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
9017 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
9019 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
9021 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
9024 def : NEONInstAlias<"vcle${p}.f16 $Qd, $Qn, $Qm",
9047 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
9049 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 1069 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); in getMveAddrModeRQOpValue() local
1071 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); in getMveAddrModeRQOpValue()
1073 return (Rn << 3) | Qm; in getMveAddrModeRQOpValue()
1088 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeQOpValue() local
1103 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits"); in getMveAddrModeQOpValue()
1105 return (Qm << 8) | Imm; in getMveAddrModeQOpValue()
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | mve-qdest-qsrc.s | 199 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
467 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 3837 unsigned Qm = fieldFromInstruction(Insn, 1, 3); in DecodeMVEVADCInstruction() local
3838 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; in DecodeMVEVADCInstruction()
3839 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) in DecodeMVEVADCInstruction()
4754 unsigned Qm = fieldFromInstruction(Insn, 0, 3); in DecodeMveAddrModeRQ() local
4758 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) in DecodeMveAddrModeRQ()
4769 unsigned Qm = fieldFromInstruction(Insn, 8, 3); in DecodeMveAddrModeQ() local
4772 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) in DecodeMveAddrModeQ()
6918 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | in DecodeMVEVCVTt1fp() local
6924 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) in DecodeMVEVCVTt1fp()
6954 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | in DecodeMVEVCMP() local
[all …]
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | invalid-armv7.txt | 435 # Qm -> bit[0] == 0, otherwise UNDEFINED
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7903 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); in validateInstruction() local
7905 if (Qd == Qm) { in validateInstruction()
|