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/llvm-project-15.0.7/llvm/unittests/Support/
H A DBranchProbabilityTest.cpp122 BP Q3(3, 4); in TEST() local
127 EXPECT_EQ(Q + H, Q3); in TEST()
128 EXPECT_EQ(Q + Q3, O); in TEST()
129 EXPECT_EQ(H + Q3, O); in TEST()
130 EXPECT_EQ(Q3 + Q3, O); in TEST()
135 EXPECT_EQ(O - Q, Q3); in TEST()
136 EXPECT_EQ(Q3 - H, Q); in TEST()
138 EXPECT_EQ(Q - Q3, Z); in TEST()
147 EXPECT_EQ(Q * 3, Q3); in TEST()
149 EXPECT_EQ(Q3 * 2, O); in TEST()
[all …]
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S27 STP Q2, Q3, [SP, #-32]!
51 LDP Q2, Q3, [SP], #32
80 STP Q2, Q3, [SP, #-32]!
103 LDP Q2, Q3, [SP], #32
133 STP Q2, Q3, [SP, #-32]!
154 LDP Q2, Q3, [SP], #32
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dpartial-reinitialization1.c34 struct Q3 { struct
47 (struct Q3){ { 1, 2, 3 }, { 4, 5, 6 } },
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
142 CCIfType<[f16, bf16, f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
225 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
H A DARMCallingConv.cpp161 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dload-dead-block.ll14 ; CHECK-NEXT: [[Q3:%.*]] = getelementptr i64, i64* [[Q]], i64 1
15 ; CHECK-NEXT: store i64 2, i64* [[Q3]], align 4
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
H A DHexagonRegisterInfo.cpp89 Q0, Q1, Q2, Q3, 0 in getCallerSavedRegs()
H A DHexagonRegisterInfo.td286 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>;
520 (add Q0, Q1, Q2, Q3)> {
/llvm-project-15.0.7/llvm/test/Transforms/OpenMP/
H A Dattributor_recursion_crash.ll23 ; CHECK-NEXT: [[Q3:%.*]] = load %struct.TS*, %struct.TS** [[GEP]], align 8
26 ; CHECK-NEXT: [[PRE2]] = phi %struct.TS* [ null, [[BB4]] ], [ [[Q3]], [[BB5]] ]
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dhvx-tmp-accum-no-erros.s26 Q3 = vcmp.eq(v0.w, v5.w) define
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECallingConv.td51 CCAssignToRegWithShadow<[Q0, Q1, Q2, Q3],
96 CCAssignToRegWithShadow<[Q0, Q1, Q2, Q3],
/llvm-project-15.0.7/llvm/test/TableGen/
H A DForeachLoop.td16 // CHECK: def Q3
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dinsert-element-build-vector-inseltpoison.ll74 ; THRESHOLD-NEXT: [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
76 ; THRESHOLD-NEXT: [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
110 ; NOTHRESHOLD-NEXT: [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
112 ; NOTHRESHOLD-NEXT: [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
152 ; MINTREESIZE-NEXT: [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
154 ; MINTREESIZE-NEXT: [[TMP8:%.*]] = insertelement <2 x float> [[TMP7]], float [[Q3]], i32 1
156 ; MINTREESIZE-NEXT: [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
H A Dinsert-element-build-vector.ll109 ; THRESHOLD-NEXT: [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
111 ; THRESHOLD-NEXT: [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
145 ; NOTHRESHOLD-NEXT: [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
147 ; NOTHRESHOLD-NEXT: [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
187 ; MINTREESIZE-NEXT: [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
189 ; MINTREESIZE-NEXT: [[TMP8:%.*]] = insertelement <2 x float> [[TMP7]], float [[Q3]], i32 1
191 ; MINTREESIZE-NEXT: [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
/llvm-project-15.0.7/llvm/test/Transforms/Inline/
H A Dret_attr_update.ll65 ; CHECK-NEXT: [[Q3:%.*]] = phi i8* [ [[R_I1]], [[RET_I]] ], [ [[GEP]], [[ORIG_I]] ]
70 ; CHECK-NEXT: ret i8* [[Q3]]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
H A DAArch64CallingConvention.td109 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
146 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
220 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
H A DAArch64PBQPRegAlloc.cpp80 case AArch64::Q3: in isOdd()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp316 {codeview::RegisterId::ARM_NQ3, ARM::Q3}, in initLLVMToCVRegMapping()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp205 {codeview::RegisterId::ARM64_Q3, AArch64::Q3}, in initLLVMToCVRegMapping()
H A DAArch64InstPrinter.cpp1253 case AArch64::Q2: Reg = AArch64::Q3; break; in getNextVectorRegister()
1254 case AArch64::Q3: Reg = AArch64::Q4; break; in getNextVectorRegister()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp94 SP::Q3, SP::Q11, ~0U, ~0U,
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td271 def Q3 : Rq<12, "F12", [D6, D7]>;
/llvm-project-15.0.7/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,

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