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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvldm-liveness.mir4 # s1 = VLDRS [r0, 1], implicit-def Q0
5 # s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
6 # s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
7 # s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
11 # imp-use of Q0, which is undefined.
H A D2010-06-29-PartialRedefFastAlloc.ll10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
11 ; redef, it cannot also get %Q0.
H A Dreg_sequence.ll176 ; CHECK: vorr q[[Q0:[0-9]+]], q[[Q1:[0-9]+]], q[[Q1:[0-9]+]]
178 ; CHECK: vuzp.32 q[[Q1]], q[[Q0]]
274 ; CHECK: vdup.32 [[Q0:q[0-9]+]], d0[0]
276 ; CHECK: vmul.f32 [[Q8:q[0-9]+]], [[Q0]], [[Q0]]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dwiden-trunc.ll10 ; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
11 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
24 ; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
25 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
38 ; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
39 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
51 ; CHECK-DAG: q[[Q0:[0-3]]] = vsetq
54 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V3]]
67 ; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
68 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
[all …]
H A Dwiden-ext.ll8 ; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
9 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V2]]
61 ; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
62 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V2]]
87 ; CHECK-DAG: q[[Q0:[0-3]]] = vsetq
90 ; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V4]]
H A Disel-widen-store.ll4 ; CHECK: q[[Q0:[0-3]]] = vsetq(r{{[0-9]+}})
5 ; CHECK: if (q[[Q0]]) vmem({{.*}}) = v
H A Dvector-predicate-typecast.ll19 ; CHECK: q[[Q0:[0-9]+]] = vand(v0,r[[R0]])
20 ; CHECK: v0 = vand(q[[Q0]],r[[R0]])
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_AArch64.S26 STP Q0, Q1, [SP, #-32]!
52 LDP Q0, Q1, [SP], #32
79 STP Q0, Q1, [SP, #-32]!
104 LDP Q0, Q1, [SP], #32
132 STP Q0, Q1, [SP, #-32]!
155 LDP Q0, Q1, [SP], #32
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv65_all.s16 if (Q0) vtmp.w=vgather(R0,M0,V0.w).w
36 if (Q0) vtmp.h=vgather(R0,M0,V1:0.w).h
91 if (Q0) vscatter(R0,M0,V1:0.w).h=V0
96 if (Q0) vtmp.h=vgather(R0,M0,V0.h).h
121 if (Q0) vscatter(R0,M0,V0.w).w=V0
131 V0.h=prefixsum(Q0)
141 V0.w=prefixsum(Q0)
146 V0.b=prefixsum(Q0)
161 if (Q0) vscatter(R0,M0,V0.h).h=V0
H A Dv62_all.s15 Q0=vsetq2(R0)
20 Q0.b=vshuffe(Q0.h,Q0.h)
25 Q0.h=vshuffe(Q0.w,Q0.w)
85 V0=vand(!Q0,R0)
90 V0|=vand(!Q0,R0)
95 V0=vand(!Q0,V0)
100 V0=vand(Q0,V0)
526 vwhist128(Q0)
531 vwhist128(Q0,#01)
541 vwhist256(Q0)
[all …]
/llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/
H A Dvmcore-amd64-minidump.bz21minidump FreeBSD/
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
90 return S[R-Hexagon::Q0]; in getStringReg()
192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
193 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmemcpy-scoped-aa.ll20 ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
22 ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
42 ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
44 ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
64 ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
66 ; CHECK-DAG: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
85 ; CHECK-DAG: global_load_dwordx2 v[[[Q0:[0-9]+]]:[[Q1:[0-9]+]]], v[2:3], off
88 ; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v[[Q0]], v[[Q1]]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Darmv8a-fpmul.s39 VFMSL.F16 Q0, D1, D2
44 VFMSL.F16 Q0, D1, D2[3]
H A Darmv8a-fpmul-error.s7 VFMSL.F16 Q0, D1, D2[4]
11 VFMSL.F16 Q0, D1, D8[0]
H A Dmve-interleave.s134 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
137 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
257 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
260 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
142 CCIfType<[f16, bf16, f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
225 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Ddifferent-vec-widths.ll18 ; SSE-NEXT: [[Q0:%.*]] = getelementptr inbounds double, double* [[Q:%.*]], i64 0
24 ; SSE-NEXT: [[TMP4:%.*]] = bitcast double* [[Q0]] to <2 x double>*
41 ; AVX-NEXT: [[Q0:%.*]] = getelementptr inbounds double, double* [[Q:%.*]], i64 0
46 ; AVX-NEXT: [[TMP4:%.*]] = bitcast double* [[Q0]] to <4 x double>*
H A Dopaque-ptr.ll7 ; CHECK-NEXT: [[Q0:%.*]] = getelementptr inbounds i64, ptr [[Q:%.*]], i64 0
9 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr [[Q0]], align 2
H A Dinsert-element-build-vector-inseltpoison.ll71 ; THRESHOLD-NEXT: [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
75 ; THRESHOLD-NEXT: [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
107 ; NOTHRESHOLD-NEXT: [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
111 ; NOTHRESHOLD-NEXT: [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
147 ; MINTREESIZE-NEXT: [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
149 ; MINTREESIZE-NEXT: [[TMP5:%.*]] = insertelement <2 x float> poison, float [[Q0]], i32 0
155 ; MINTREESIZE-NEXT: [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
H A Dinsert-element-build-vector.ll106 ; THRESHOLD-NEXT: [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
110 ; THRESHOLD-NEXT: [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
142 ; NOTHRESHOLD-NEXT: [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
146 ; NOTHRESHOLD-NEXT: [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
182 ; MINTREESIZE-NEXT: [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
184 ; MINTREESIZE-NEXT: [[TMP5:%.*]] = insertelement <2 x float> poison, float [[Q0]], i32 0
190 ; MINTREESIZE-NEXT: [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-return-vector.ll3 ; 2x64 vector should be returned in Q0.
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVECallingConv.td51 CCAssignToRegWithShadow<[Q0, Q1, Q2, Q3],
96 CCAssignToRegWithShadow<[Q0, Q1, Q2, Q3],
/llvm-project-15.0.7/llvm/test/TableGen/
H A DForeachLoop.td13 // CHECK: def Q0
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,

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