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Searched refs:PtrReg (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp320 Register PtrReg = Store.getPointerReg(); in applySplitStoreZero128() local
322 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
327 B.buildStore(Zero, PtrReg, *LowMMO); in applySplitStoreZero128()
H A DAArch64InstructionSelector.cpp2815 const Register PtrReg = LdSt.getPointerReg(); in select() local
2816 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2820 assert(MRI.getType(PtrReg).isPointer() && in select()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp413 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
414 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]); in lowerParameter()
433 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
543 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
544 lowerParameterPtr(PtrReg, B, ArgOffset); in lowerFormalArgumentsKernel()
546 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
H A DAMDGPURegisterBankInfo.cpp1075 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1086 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1090 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1094 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
1111 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0); in applyMappingLoad()
3450 Register PtrReg) const { in getValueMappingForPtr()
3451 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
3459 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3470 Register PtrReg = MI.getOperand(1).getReg(); in getInstrMappingForLoad() local
3471 LLT PtrTy = MRI.getType(PtrReg); in getInstrMappingForLoad()
[all …]
H A DAMDGPULegalizerInfo.cpp2631 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
2632 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
2637 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
2682 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2690 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2695 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2732 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
2736 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
2746 .addUse(PtrReg) in legalizeAtomicCmpXChg()
H A DAMDGPUInstructionSelector.cpp3924 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
3931 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp708 Register PtrReg = LoadMI->getPointerReg(); in matchCombineLoadWithAndMask() local
740 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
748 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO); in matchCombineLoadWithAndMask()
2037 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2045 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2047 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2050 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2055 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2062 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2067 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
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H A DLegalizerHelper.cpp1054 Register PtrReg = LoadMI.getPointerReg(); in narrowScalar() local
1061 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
2929 Register PtrReg = LoadMI.getPointerReg(); in lowerLoad() local
2967 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
3029 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
3033 PtrReg, *LargeMMO); in lowerLoad()
3071 Register PtrReg = StoreMI.getPointerReg(); in lowerStore() local
3099 MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); in lowerStore()
3146 LLT PtrTy = MRI.getType(PtrReg); in lowerStore()
3150 MIRBuilder.buildPtrAdd(PtrTy, PtrReg, OffsetCst); in lowerStore()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11603 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
11665 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
11670 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
11691 .addReg(PtrReg); in EmitPartwordAtomicBinary()
11735 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12610 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
12680 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
12685 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
12717 .addReg(PtrReg); in EmitInstrWithCustomInserter()
12741 .addReg(PtrReg); in EmitInstrWithCustomInserter()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4842 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
4843 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()