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Searched refs:ProcResource (Results 1 – 25 of 58) sorted by relevance

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/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DResourcePressureView.cpp29 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in ResourcePressureView() local
30 unsigned NumUnits = ProcResource.NumUnits; in ResourcePressureView()
32 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in ResourcePressureView()
36 R2VIndex += ProcResource.NumUnits; in ResourcePressureView()
73 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printColumnNames() local
74 unsigned NumUnits = ProcResource.NumUnits; in printColumnNames()
76 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printColumnNames()
112 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printResourcePressurePerIter() local
113 unsigned NumUnits = ProcResource.NumUnits; in printResourcePressurePerIter()
115 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printResourcePressurePerIter()
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H A DSchedulerStatistics.cpp141 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printSchedulerUsage() local
142 if (ProcResource.BufferSize <= 0) in printSchedulerUsage()
147 double AlmostFullThreshold = (double)(ProcResource.BufferSize * 4) / 5; in printSchedulerUsage()
151 FOS << ProcResource.Name; in printSchedulerUsage()
160 BU.MaxUsedSlots == static_cast<unsigned>(ProcResource.BufferSize)) in printSchedulerUsage()
166 FOS << ProcResource.BufferSize << '\n'; in printSchedulerUsage()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td39 def FalkorUnitB : ProcResource<1>; // Branch
40 def FalkorUnitLD : ProcResource<1>; // Load pipe
41 def FalkorUnitSD : ProcResource<1>; // Store data
42 def FalkorUnitST : ProcResource<1>; // Store pipe
44 def FalkorUnitY : ProcResource<1>; // Simple arithmetic
45 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
47 def FalkorUnitVSD : ProcResource<1>; // Vector store data
48 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
49 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
51 def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector
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H A DAArch64SchedExynosM5.td38 def M5UnitA : ProcResource<2>; // Simple integer
44 def M5UnitF : ProcResource<2>; // CRC (inside C)
45 def M5UnitB : ProcResource<1>; // Branch
46 def M5UnitL0 : ProcResource<1>; // Load
47 def M5UnitS0 : ProcResource<1>; // Store
48 def M5PipeLS : ProcResource<1>; // Load/Store
50 def M5UnitL1 : ProcResource<1>;
51 def M5UnitS1 : ProcResource<1>;
53 def M5PipeF0 : ProcResource<1>; // FP #0
66 def M5PipeF1 : ProcResource<1>; // FP #1
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H A DAArch64SchedExynosM3.td39 def M3UnitA : ProcResource<2>; // Simple integer
42 def M3UnitB : ProcResource<2>; // Branch
43 def M3UnitL : ProcResource<2>; // Load
44 def M3UnitS : ProcResource<1>; // Store
45 def M3PipeF0 : ProcResource<1>; // FP #0
48 def M3UnitFADD0 : ProcResource<1>; // Simple FP
56 def M3PipeF1 : ProcResource<1>; // FP #1
59 def M3UnitFADD1 : ProcResource<1>; // Simple FP
62 def M3UnitFST0 : ProcResource<1>; // FP store
69 def M3PipeF2 : ProcResource<1>; // FP #2
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H A DAArch64SchedExynosM4.td38 def M4UnitA : ProcResource<2>; // Simple integer
44 def M4UnitB : ProcResource<2>; // Branch
45 def M4UnitL0 : ProcResource<1>; // Load
46 def M4UnitS0 : ProcResource<1>; // Store
47 def M4PipeLS : ProcResource<1>; // Load/Store
49 def M4UnitL1 : ProcResource<1>;
50 def M4UnitS1 : ProcResource<1>;
52 def M4PipeF0 : ProcResource<1>; // FP #0
65 def M4PipeF1 : ProcResource<1>; // FP #1
71 def M4UnitFST0 : ProcResource<1>; // FP store
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H A DAArch64SchedKryo.td42 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
43 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
44 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
45 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
54 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
55 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
H A DAArch64SchedA53.td39 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
42 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
43 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
44 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
45 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
46 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
47 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
48 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
H A DAArch64SchedThunderX.td37 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
38 def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
39 def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
40 def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
41 def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch
42 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
43 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
H A DAArch64SchedCyclone.td31 def CyUnitI : ProcResource<4> {
36 def CyUnitB : ProcResource<2> {
42 def CyUnitBR : ProcResource<1> {
48 def CyUnitIS : ProcResource<2> {
54 def CyUnitIM : ProcResource<1> {
60 def CyUnitID : ProcResource<1> {
70 def CyUnitLS : ProcResource<2> {
75 def CyUnitV : ProcResource<3> {
79 def CyUnitVM : ProcResource<2> {
84 def CyUnitVD : ProcResource<1> {
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H A DAArch64SchedA55.td41 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since the
44 def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
45 def CortexA55UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC, 64-bi wide
46 def CortexA55UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division, not pipelined
47 def CortexA55UnitLd : ProcResource<1> { let BufferSize = 0; } // Load pipe
48 def CortexA55UnitSt : ProcResource<1> { let BufferSize = 0; } // Store pipe
49 def CortexA55UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
54 def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
55 def CortexA55UnitFPMAC : ProcResource<2> { let BufferSize = 0; } // FP MAC
56 def CortexA55UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP Div/SQRT, 64/128
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td88 def ALU : ProcResource<4>;
89 def ALUE : ProcResource<2> {
99 def DIV : ProcResource<2>;
102 def DP : ProcResource<4>;
103 def DPE : ProcResource<2> {
107 def DPO : ProcResource<2> {
113 def LS : ProcResource<4>;
116 def PM : ProcResource<2>;
119 def DFU : ProcResource<1>;
122 def BR : ProcResource<1> {
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H A DPPCScheduleP10.td48 def P10_BF : ProcResource<4>; // Four Binary Floating Point pipelines.
49 def P10_BR : ProcResource<2>; // Two Branch pipelines.
50 def P10_CY : ProcResource<4>; // Four Crypto pipelines.
51 def P10_DF : ProcResource<1>; // One Decimal Floating Point pipelines.
54 def P10_FX : ProcResource<4>; // Four ALU pipelines.
55 def P10_LD : ProcResource<2>; // Two Load pipelines.
57 def P10_PM : ProcResource<4>; // Four 128-bit permute (PM) pipelines.
58 def P10_ST : ProcResource<2>; // Two ST-D pipelines.
64 def P10_ANY_SLOT : ProcResource<8>;
69 def P10_EVEN_SLOT : ProcResource<4>;
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/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp34 const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index); in execute() local
35 unsigned NumUnits = ProcResource.NumUnits; in execute()
36 if (!ProcResource.SubUnitsIdxBegin) { in execute()
50 unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1]; in execute()
/llvm-project-15.0.7/llvm/tools/llvm-mca/
H A DPipelinePrinter.cpp86 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in getJSONTargetInfo() local
87 unsigned NumUnits = ProcResource.NumUnits; in getJSONTargetInfo()
88 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in getJSONTargetInfo()
92 std::string ResourceName = ProcResource.Name; in getJSONTargetInfo()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td29 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
33 def RocketUnitALU : ProcResource<1>; // Int ALU
34 def RocketUnitIMul : ProcResource<1>; // Int Multiply
35 def RocketUnitMem : ProcResource<1>; // Load/Store
36 def RocketUnitB : ProcResource<1>; // Branch
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
42 def RocketUnitIDiv : ProcResource<1>; // Int Division
43 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
H A DRISCVSchedSiFive7.td30 def SiFive7PipeA : ProcResource<1>;
31 def SiFive7PipeB : ProcResource<1>;
35 def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
36 def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSISchedule.td95 def HWBranch : ProcResource<1> {
98 def HWExport : ProcResource<1> {
101 def HWLGKM : ProcResource<1> {
104 def HWSALU : ProcResource<1> {
107 def HWVMEM : ProcResource<1> {
110 def HWVALU : ProcResource<1> {
113 def HWTransVALU : ProcResource<1> { // Transcendental VALU
116 def HWRC : ProcResource<1> { // Register destination cache
119 def HWXDL : ProcResource<1> { // MFMA CU
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetPfmCounters.td21 // Issue counters can be tied to a ProcResource
24 // The name of the ProcResource on which uops are issued. This is used by
27 // ProcResource.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td38 def M7UnitLoadL : ProcResource<1> { let BufferSize = 0; }
39 def M7UnitLoadH : ProcResource<1> { let BufferSize = 0; }
41 def M7UnitStore : ProcResource<1> { let BufferSize = 0; }
42 def M7UnitALU : ProcResource<2>;
43 def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; }
44 def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; }
45 def M7UnitMAC : ProcResource<1> { let BufferSize = 0; }
46 def M7UnitBranch : ProcResource<1> { let BufferSize = 0; }
47 def M7UnitVFP : ProcResource<1> { let BufferSize = 0; }
48 def M7UnitVPortL : ProcResource<1> { let BufferSize = 0; }
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td32 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
33 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
47 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
48 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
49 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
50 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
52 def P5600AL2Div : ProcResource<1>;
54 def P5600CTISTD : ProcResource<1>;
231 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
236 def P5600FPUDivSqrt : ProcResource<2>;
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td54 def ALU : ProcResource<1> { let BufferSize = 0; }
55 def LdSt : ProcResource<1> { let BufferSize = 0; }
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleBdVer2.td50 def PdEX0 : ProcResource<1>; // ALU, Integer Pipe0
63 def PdFPU0 : ProcResource<1>; // Vector/FPU Pipe0
64 def PdFPU1 : ProcResource<1>; // Vector/FPU Pipe1
65 def PdFPU2 : ProcResource<1>; // Vector/FPU Pipe2
66 def PdFPU3 : ProcResource<1>; // Vector/FPU Pipe3
133 def PdLoad : ProcResource<2> {
141 def PdStore : ProcResource<1> {
166 def PdFPMMA : ProcResource<1>; // PdFPU0
169 def PdFPCVT : ProcResource<1>; // PdFPU0
172 def PdFPXBR : ProcResource<1>; // PdFPU1
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H A DX86ScheduleSLM.td34 def SLM_IEC_RSV0 : ProcResource<1>;
35 def SLM_IEC_RSV1 : ProcResource<1>;
36 def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
37 def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
38 def SLM_MEC_RSV : ProcResource<1>;
44 def SLMDivider : ProcResource<1>;
45 def SLMFPMultiplier : ProcResource<1>;
46 def SLMFPDivider : ProcResource<1>;
H A DX86ScheduleBtVer2.td35 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
37 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
38 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
88 def JDiv : ProcResource<1>; // integer division
89 def JMul : ProcResource<1>; // integer multiplication
90 def JVALU0 : ProcResource<1>; // vector integer
91 def JVALU1 : ProcResource<1>; // vector integer
92 def JVIMUL : ProcResource<1>; // vector integer multiplication
93 def JSTC : ProcResource<1>; // vector store/convert
94 def JFPM : ProcResource<1>; // FP multiplication
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