Searched refs:PrevInstr (Results 1 – 4 of 4) sorted by relevance
207 MachineInstr *PrevInstr = nullptr; in runOnBasicBlock() local211 PrevInstr = getLastNonPseudo(MBB, TII); in runOnBasicBlock()216 if (PrevInstr) { in runOnBasicBlock()217 LLVM_DEBUG(dbgs() << " PrevInstr: " << *PrevInstr in runOnBasicBlock()220 << isFirstInstructionInSequence(PrevInstr) << "\n" in runOnBasicBlock()223 if (isFirstInstructionInSequence(PrevInstr) && in runOnBasicBlock()231 PrevInstr = CurrInstr; in runOnBasicBlock()
326 const Instr *PrevInstr = Analysis.getPrevInstructionSequential(ChildMeta); in buildFlowGraphImpl() local327 if (PrevInstr && Analysis.willTrapOnCFIViolation(*PrevInstr)) { in buildFlowGraphImpl()328 Result.IntermediateNodes[PrevInstr->VMAddress] = Address; in buildFlowGraphImpl()
2192 MCInst &PrevInstr = *PrevII; in analyzeIndirectBranch() local2193 const MCInstrDesc &PrevInstrDesc = Info->get(PrevInstr.getOpcode()); in analyzeIndirectBranch()2195 if (!PrevInstrDesc.hasDefOfPhysReg(PrevInstr, R1, *RegInfo)) in analyzeIndirectBranch()2198 if (isMoveMem2Reg(PrevInstr)) { in analyzeIndirectBranch()2199 MemLocInstr = &PrevInstr; in analyzeIndirectBranch()2202 if (isADD64rr(PrevInstr)) { in analyzeIndirectBranch()2203 unsigned R2 = PrevInstr.getOperand(2).getReg(); in analyzeIndirectBranch()
1998 MCInst *PrevInstr = PrevBB->getLastNonPseudoInstr(); in buildCFG() local1999 assert(PrevInstr && "no previous instruction for a fall through"); in buildCFG()2001 !MIB->isUnconditionalBranch(*PrevInstr) && in buildCFG()2002 !MIB->getConditionalTailCall(*PrevInstr) && in buildCFG()2003 !MIB->isReturn(*PrevInstr)) { in buildCFG()