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Searched refs:PostRA (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp3502 bool PostRA = !MRI->isSSA(); in foldFrameOffset() local
3506 if (!PostRA) in foldFrameOffset()
4253 if (PostRA) { in instrHasImmForm()
4267 if (PostRA) { in instrHasImmForm()
4285 if (PostRA) { in instrHasImmForm()
4299 if (PostRA) { in instrHasImmForm()
4550 if (PostRA) in simplifyToLI()
4708 if (!PostRA) { in simplifyToLI()
4760 if (PostRA) in transformToNewImmFormFedByAdd()
4892 bool PostRA = !MRI.isSSA(); in transformToImmFormFedByAdd() local
[all …]
H A DPPCInstrInfo.h741 bool PostRA) const;
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2011-02-07-AntidepClobber.ll2 ; PR8986: PostRA antidependence breaker must respect "earlyclobber".
H A DO3-pipeline.ll141 ; CHECK-NEXT: PostRA Machine Sink
167 ; CHECK-NEXT: PostRA Machine Instruction Scheduler
/llvm-project-15.0.7/llvm/test/Feature/
H A Doptnone-llc.ll57 ; LLC-MORE: Skipping pass 'PostRA Machine Instruction Scheduler'
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpostra-ignore-dbg-instrs.mir12 # The code generates a COPY instruction which the PostRA Machine Sink pass will
H A Dopt-pipeline.ll163 ; CHECK-NEXT: PostRA Machine Sink
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineSink.cpp1059 bool PostRA = MRI.getNumVirtRegs() == 0; in attemptDebugCopyProp() local
1068 if (arePhysRegs != PostRA) in attemptDebugCopyProp()
1073 if (!PostRA) in attemptDebugCopyProp()
1082 if (PostRA && Reg != DstMO->getReg()) in attemptDebugCopyProp()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DO3-pipeline.ll174 ; CHECK-NEXT: PostRA Machine Sink
193 ; CHECK-NEXT: PostRA Machine Instruction Scheduler
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DO3-pipeline.ll183 ; CHECK-NEXT: PostRA Machine Sink
205 ; CHECK-NEXT: PostRA Machine Instruction Scheduler
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsink-after-control-flow-postra.mir4 # Ensure that PostRA Machine Sink does not sink instructions
H A Dllc-pipeline.ll355 ; GCN-O1-NEXT: PostRA Machine Sink
373 ; GCN-O1-NEXT: PostRA Machine Instruction Scheduler
645 ; GCN-O1-OPTS-NEXT: PostRA Machine Sink
663 ; GCN-O1-OPTS-NEXT: PostRA Machine Instruction Scheduler
937 ; GCN-O2-NEXT: PostRA Machine Sink
955 ; GCN-O2-NEXT: PostRA Machine Instruction Scheduler
1242 ; GCN-O3-NEXT: PostRA Machine Sink
1260 ; GCN-O3-NEXT: PostRA Machine Instruction Scheduler
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A DO3-pipeline.ll131 ; CHECK-NEXT: PostRA Machine Sink
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td25 let PostRAScheduler = 1; // Use PostRA scheduler.
H A DAArch64SchedA55.td29 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
H A DAArch64SchedThunderX2T99.td25 let PostRAScheduler = 1; // Using PostRA sched.
H A DAArch64SchedThunderX3T110.td24 let PostRAScheduler = 1; // Using PostRA sched.
H A DAArch64SchedA64FX.td20 let PostRAScheduler = 1; // Using PostRA sched.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA9.td15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
2177 // Define VLDM/VSTM PostRA Resources.
2195 // VLDM PostRA Variants. These variants expand A9WriteLMfpPostRA into a
H A DARMScheduleSwift.td15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td1826 // during ISelLowering, which produces the PostRA version of this instruction.