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Searched refs:Port (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/Debuginfod/
H A DHTTPServerTests.cpp93 unsigned Port = *PortOrErr; in TEST_F() local
96 std::string Url = "http://localhost:" + utostr(Port); in TEST_F()
117 unsigned Port = *PortOrErr; in TEST_F() local
120 std::string Url = "http://localhost:" + utostr(Port); in TEST_F()
136 unsigned Port = *PortOrErr; in TEST_F() local
139 std::string Url = "http://localhost:" + utostr(Port); in TEST_F()
168 unsigned Port = *PortOrErr; in TEST_F() local
204 unsigned Port = *PortOrErr; in TEST_F() local
221 unsigned Port = *PortOrErr; in TEST_F() local
258 unsigned Port = *PortOrErr; in TEST_F() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DTensorSpec.h57 int Port = 0) {
58 return TensorSpec(Name, Port, getDataType<T>(), sizeof(T), Shape);
62 int port() const { return Port; } in port()
67 return Name == Other.Name && Port == Other.Port && Type == Other.Type &&
85 TensorSpec(const std::string &Name, int Port, TensorType Type,
91 int Port = 0; variable
/llvm-project-15.0.7/llvm/tools/llvm-debuginfod/
H A Dllvm-debuginfod.cpp33 Port("p", cl::init(0), variable
82 if (!Port) in main()
83 Port = ExitOnErr(Server.Server.bind(HostInterface.c_str())); in main()
85 ExitOnErr(Server.Server.bind(Port, HostInterface.c_str())); in main()
87 Log.push("Listening on port " + Twine(Port).str()); in main()
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/google/
H A DIntegerTypesCheck.cpp129 const StringRef Port = "unsigned short port"; in check() local
131 if (!std::strncmp(Data, Port.data(), Port.size()) && in check()
132 !isAsciiIdentifierContinue(Data[Port.size()])) in check()
/llvm-project-15.0.7/llvm/lib/Debuginfod/
H A DHTTPServer.cpp124 Port = ListenPort; in bind()
133 return Port = ListenPort; in bind()
137 if (!Port) in listen()
149 Port = 0; in stop()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DTensorSpec.cpp38 TensorSpec::TensorSpec(const std::string &Name, int Port, TensorType Type, in SUPPORTED_TENSOR_TYPES()
40 : Name(Name), Port(Port), Type(Type), Shape(Shape), in SUPPORTED_TENSOR_TYPES()
/llvm-project-15.0.7/llvm/include/llvm/Debuginfod/
H A DHTTPServer.h92 unsigned Port = 0; variable
108 Error bind(unsigned Port, const char *HostInterface = "0.0.0.0");
/llvm-project-15.0.7/llvm/tools/llvm-jitlink/llvm-jitlink-executor/
H A Dllvm-jitlink-executor.cpp148 int Port = 0; in main() local
149 if (PortStr.getAsInteger(10, Port)) in main()
/llvm-project-15.0.7/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/
H A DRemoteJITUtils.cpp205 int Port = 0; in connectTCPSocket() local
206 if (PortStr.getAsInteger(10, Port)) in connectTCPSocket()
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/
H A Dtargets.gni10 # FIXME: Port the remaining targets.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td38 // Port 0: ALU.
41 // Port 1: ALU.
44 // Port 2: ALU/Branch.
47 // Port 3: ALU/Branch.
50 // Port 4: Load/Store.
53 // Port 5: Load/store.
56 // Port 6: FP/Neon/SIMD/Crypto.
59 // Port 7: FP/Neon/SIMD/Crypto.
62 // Port 8: FP/Neon/SIMD/Crypto.
65 // Port 9: FP/Neon/SIMD/Crypto.
[all …]
H A DAArch64SchedThunderX2T99.td40 // Port 0: ALU, FP/SIMD.
43 // Port 1: ALU, FP/SIMD, integer mul/div.
46 // Port 2: ALU, Branch.
49 // Port 3: Store data.
52 // Port 4: Load/store.
55 // Port 5: Load/store.
H A DAArch64SchedA64FX.td36 // Port 0
39 // Port 1
42 // Port 2
45 // Port 3
48 // Port 4
51 // Port 5
54 // Port 6
57 // Port 7
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/
H A Downing-memory.rst73 // Port legacy code for better resource-safety
/llvm-project-15.0.7/llvm/tools/llvm-jitlink/
H A Dllvm-jitlink.cpp959 int Port = 0; in connectToExecutor()
960 if (PortStr.getAsInteger(10, Port)) in connectToExecutor()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleZnver1.td136 // Register variant takes 1-cycle on Execution Port.
157 // Register variant takes 1-cycle on Execution Port.
H A DX86ScheduleZnver2.td135 // Register variant takes 1-cycle on Execution Port.
156 // Register variant takes 1-cycle on Execution Port.
H A DX86SchedSkylakeClient.td35 // Port 4 gets the data half of stores. Store data can be available later than
39 // stores. Port 7 can handle address calculations.
H A DX86SchedBroadwell.td35 // Port 4 gets the data half of stores. Store data can be available later than
39 // stores. Port 7 can handle address calculations.
H A DX86SchedHaswell.td40 // Port 4 gets the data half of stores. Store data can be available later than
44 // stores. Port 7 can handle address calculations.
H A DX86SchedSkylakeServer.td35 // Port 4 gets the data half of stores. Store data can be available later than
39 // stores. Port 7 can handle address calculations.
H A DX86SchedSandyBridge.td48 // Port 4 gets the data half of stores. Store data can be available later than
/llvm-project-15.0.7/openmp/docs/design/
H A DRuntimes.rst1075 * ``LIBOMPTARGET_RPC_ADDRESS=<Address>:<Port>``