Searched refs:PackVT (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEInstrPatternsVec.td | 144 multiclass Packing<ValueType PackVT> {
146 def : Pat<(v256i32 (vec_unpack_lo PackVT:$vp, (i32 srcvalue))),
148 def : Pat<(v256f32 (vec_unpack_hi PackVT:$vp, (i32 srcvalue))),
152 def : Pat<(v256f32 (vec_unpack_lo PackVT:$vp, i32:$avl)),
154 def : Pat<(v256i32 (vec_unpack_hi PackVT:$vp, i32:$avl)),
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5850 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16; in lowerVECTOR_SHUFFLE() local
5851 EVT EltVT = PackVT.getVectorElementType(); in lowerVECTOR_SHUFFLE()
5871 PackVT, SVN->getOperand(VecIdx), in lowerVECTOR_SHUFFLE()
5889 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 })); in lowerVECTOR_SHUFFLE()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 12552 auto MatchPACK = [&](SDValue N1, SDValue N2, MVT PackVT) { in matchShuffleWithPACK() argument
12553 unsigned NumSrcBits = PackVT.getScalarSizeInBits(); in matchShuffleWithPACK()
12570 SrcVT = PackVT; in matchShuffleWithPACK()
12583 SrcVT = PackVT; in matchShuffleWithPACK()
12593 MVT PackVT = MVT::getVectorVT(PackSVT, NumElts >> NumStages); in matchShuffleWithPACK() local
12599 if (MatchPACK(V1, V2, PackVT)) in matchShuffleWithPACK()
12606 if (MatchPACK(V1, V1, PackVT)) in matchShuffleWithPACK()
12616 MVT PackVT; in lowerShuffleWithPACK() local
12621 if (!matchShuffleWithPACK(VT, PackVT, V1, V2, PackOpcode, Mask, DAG, in lowerShuffleWithPACK()
12625 unsigned CurrentEltBits = PackVT.getScalarSizeInBits(); in lowerShuffleWithPACK()
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