| /llvm-project-15.0.7/llvm/lib/MCA/Stages/ |
| H A D | InOrderIssueStage.cpp | 49 : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU), in InOrderIssueStage()
103 static unsigned checkRegisterHazard(const RegisterFile &PRF, in checkRegisterHazard() argument
119 if (unsigned Cycles = checkRegisterHazard(PRF, STI, IR)) { in canExecute()
163 PRF.addRegisterRead(RS, STI); in addRegisterReadWrite()
166 PRF.addRegisterWrite(WriteRef(SourceIndex, &WS), UsedRegs); in addRegisterReadWrite()
228 addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs); in tryIssue()
262 PRF.onInstructionExecuted(&IS); in tryIssue()
297 PRF.onInstructionExecuted(&IS); in updateIssuedInst()
342 PRF.removeRegisterWrite(WS, FreedRegs); in retireInstruction()
385 PRF.cycleStart(); in cycleStart()
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| H A D | DispatchStage.cpp | 33 CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) { in DispatchStage()
51 const unsigned RegisterMask = PRF.isAvailable(RegDefs); in checkPRF()
98 if (PRF.tryEliminateMoveOrSwap(IS.getDefs(), IS.getUses())) in dispatch()
112 PRF.addRegisterRead(RS, STI); in dispatch()
118 SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles()); in dispatch()
120 PRF.addRegisterWrite(WriteRef(IR.getSourceIndex(), &WS), RegisterFiles); in dispatch()
147 SmallVector<unsigned, 8> RegisterFiles(PRF.getNumRegisterFiles(), 0U); in cycleStart()
181 PRF.dump(); in dump()
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| H A D | RetireStage.cpp | 26 PRF.cycleStart(); in cycleStart()
45 PRF.cycleEnd(); in cycleEnd()
52 PRF.onInstructionExecuted(&IS); in execute()
62 llvm::SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles()); in notifyInstructionRetired()
70 PRF.removeRegisterWrite(WS, FreedRegs); in notifyInstructionRetired()
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| /llvm-project-15.0.7/llvm/lib/MCA/ |
| H A D | Context.cpp | 41 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); in createDefaultPipeline() local
49 std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF); in createDefaultPipeline()
52 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); in createDefaultPipeline()
56 addHardwareUnit(std::move(PRF)); in createDefaultPipeline()
76 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); in createInOrderPipeline() local
82 auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU); in createInOrderPipeline()
86 addHardwareUnit(std::move(PRF)); in createInOrderPipeline()
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/ |
| H A D | RetireStage.h | 31 RegisterFile &PRF; variable
39 : RCU(R), PRF(F), LSU(LS) {} in RetireStage()
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| H A D | InOrderIssueStage.h | 56 RegisterFile &PRF; variable
115 InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
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| H A D | DispatchStage.h | 56 RegisterFile &PRF; variable
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 311 void setPRF(unsigned PRF) { PRFID = PRF; } in setPRF() argument
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleBtVer2.td | 40 // The Integer PRF for Jaguar is 64 entries, and it holds the architectural and
58 // The PRF in the floating point unit can eliminate a move from a MMX or SSE
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| H A D | X86ScheduleZnver1.td | 99 // The Integer PRF for Zen is 168 entries, and it holds the architectural and
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| H A D | X86ScheduleZnver2.td | 100 // The Integer PRF for Zen is 168 entries, and it holds the architectural and
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| H A D | X86ScheduleZnver3.td | 160 // The integer physical register file (PRF) consists of 192 registers.
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| /llvm-project-15.0.7/llvm/docs/CommandGuide/ |
| H A D | llvm-mca.rst | 791 file (PRF) used by the pipeline is presented in this table. In the case of AMD
798 that the floating point PRF was the only register file used for the example, and
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedNeoverseN2.td | 2262 def : InstRW<[N2Write_4cyc_1L], (instregex "^PRF[BHWD]")>;
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