Searched refs:PPRRegClass (Results 1 – 6 of 6) sorted by relevance
770 } else if (AArch64::PPRRegClass.contains(Reg)) { in PrintAsmOperand()771 RegClass = &AArch64::PPRRegClass; in PrintAsmOperand()
53 if (AArch64::PPRRegClass.contains(Reg)) in regNeedsCFI()
2558 else if (AArch64::PPRRegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()3025 if (AArch64::PPRRegClass.contains(Reg) || in determineCalleeSaves()3192 AArch64::PPRRegClass.contains(CS.getReg())) { in getSVECalleeSaveSlotRange()
3498 if (AArch64::PPRRegClass.contains(DestReg) && in copyPhysReg()3499 AArch64::PPRRegClass.contains(SrcReg)) { in copyPhysReg()3804 else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()3958 else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
339 addRegisterClass(MVT::nxv1i1, &AArch64::PPRRegClass); in AArch64TargetLowering()340 addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass); in AArch64TargetLowering()341 addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass); in AArch64TargetLowering()342 addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass); in AArch64TargetLowering()343 addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass); in AArch64TargetLowering()5854 RC = &AArch64::PPRRegClass; in LowerFormalArguments()6534 AArch64::PPRRegClass.contains(Loc.getLocReg()); in LowerCall()9116 : std::make_pair(0U, &AArch64::PPRRegClass); in getRegForInlineAsmConstraint()
4700 auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID]; in validateInstruction() local4707 PPRRegClass.contains(Inst.getOperand(i).getReg())) { in validateInstruction()