| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 2409 def : Pat<(nxv16i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
2410 def : Pat<(nxv16i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
2411 def : Pat<(nxv16i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
2412 def : Pat<(nxv16i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
2413 def : Pat<(nxv8i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
2414 def : Pat<(nxv8i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
2442 def : Pat<(nxv16i1 (and PPR:$Ps1, PPR:$Ps2)),
2444 def : Pat<(nxv8i1 (and PPR:$Ps1, PPR:$Ps2)),
2446 def : Pat<(nxv4i1 (and PPR:$Ps1, PPR:$Ps2)),
2448 def : Pat<(nxv2i1 (and PPR:$Ps1, PPR:$Ps2)),
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| H A D | AArch64RegisterInfo.td | 879 def PPR : PPRClass<15>;
891 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>;
892 def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>;
893 def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
894 def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
895 def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
897 def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
898 def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
899 def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
900 def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
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| H A D | SVEInstrFormats.td | 7160 (!cast<Instruction>(NAME # _UXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
7162 (!cast<Instruction>(NAME # _SXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
7208 def : Pat<(nxv4i32 (op (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt)),
7209 (!cast<Instruction>(NAME # _IMM) PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
7529 (!cast<Instruction>(NAME # _UXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
7531 (!cast<Instruction>(NAME # _SXTW) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
7549 def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
7567 def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
7568 (!cast<Instruction>(NAME) PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
7613 def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt)),
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| H A D | AArch64FrameLowering.cpp | 2483 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
2491 case PPR: in getScale()
2503 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable()
2559 RPI.Type = RegPairInfo::PPR; in computeCalleeSaveRegisterPairs()
2584 case RegPairInfo::PPR: in computeCalleeSaveRegisterPairs()
2765 case RegPairInfo::PPR: in spillCalleeSavedRegisters()
2812 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) in spillCalleeSavedRegisters()
2869 case RegPairInfo::PPR: in restoreCalleeSavedRegisters()
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| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | access-control-check.cpp | 9 int PPR(); // expected-note {{declared private here}}
14 int PR() { return iP + PPR(); } // expected-error 2 {{private member of 'P'}} in PR()
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | nested-base-member-access.cpp | 32 void PPR() { printf("iP = %d\n", iP); } in PPR() function
39 this->MPR(); this->PPR(); this->QPR(); in PR()
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| H A D | constructor-init.cpp | 18 void PPR() {printf("iP = %d\n", iP); }; in PPR() function
39 PPR(); in PR()
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| /llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/ |
| H A D | note-core.test | 75 …delf --notes %t15.o | FileCheck %s --check-prefix=CHECK-GNU -DDESC="NT_PPC_PPR (ppc PPR register)"
76 …dobj --notes %t15.o | FileCheck %s --check-prefix=CHECK-LLVM -DDESC="NT_PPC_PPR (ppc PPR register)"
125 ….o | FileCheck %s --check-prefix=CHECK-GNU -DDESC="NT_PPC_TM_CPPR (ppc checkpointed PPR register)"
126 ….o | FileCheck %s --check-prefix=CHECK-LLVM -DDESC="NT_PPC_TM_CPPR (ppc checkpointed PPR register)"
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | named-vector-shuffle-reverse-sve.ll | 8 ; VECTOR_REVERSE - PPR
|