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Searched refs:PFALSE (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-pfalse-machine-cse.mir14 ; CHECK-NEXT: [[PFALSE:%[0-9]+]]:ppr = PFALSE
15 ; CHECK-NEXT: [[UZP1_PPP_B:%[0-9]+]]:ppr = UZP1_PPP_B [[COPY]], [[PFALSE]]
16 ; CHECK-NEXT: [[UZP1_PPP_B1:%[0-9]+]]:ppr = UZP1_PPP_B killed [[UZP1_PPP_B]], [[PFALSE]]
20 %2:ppr = PFALSE
22 %4:ppr = PFALSE
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h71 PFALSE, enumerator
H A DHexagonISelLowering.cpp1908 case HexagonISD::PFALSE: return "HexagonISD::PFALSE"; in getTargetNodeName()
2812 return DAG.getNode(HexagonISD::PFALSE, dl, VecTy); in LowerBUILD_VECTOR()
3312 case HexagonISD::PFALSE: in PerformDAGCombine()
H A DHexagonPatterns.td97 def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp811 BuildMI(MBB, MBBI, DL, TII.get(AArch64::PFALSE), PReg); in emitZeroCallUsedRegs()
H A DAArch64SchedNeoverseN2.td1534 def : InstRW<[N2Write_2cyc_1M], (instregex "^PFALSE$", "^PTRUE_[BHSD]$")>;
H A DAArch64SchedA64FX.td3309 def : InstRW<[A64FXWrite_3Cyc_GI1], (instrs PFALSE)>;
H A DAArch64SVEInstrInfo.td824 defm PFALSE : sve_int_pfalse<0b000000, "pfalse">;