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Searched refs:OutRegs (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.h400 std::set<unsigned> &OutRegs);
474 std::set<unsigned> OutRegs; in getOutRegs() local
476 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
478 return OutRegs; in getOutRegs()
H A DSIMachineScheduler.cpp1478 const std::set<unsigned> &OutRegs = Block->getOutRegs(); in SIScheduleBlockScheduler() local
1480 if (OutRegs.find(Reg) == OutRegs.end()) in SIScheduleBlockScheduler()
1702 std::set<unsigned> &OutRegs) { in checkRegUsageImpact() argument
1718 for (Register Reg : OutRegs) { in checkRegUsageImpact()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DFastISel.h95 SmallVector<Register, 16> OutRegs; member
191 OutRegs.clear(); in clearOuts()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp3159 auto &OutRegs = CLI.OutRegs; in fastLowerCall() local
3386 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3511 for (auto Reg : OutRegs) in fastLowerCall()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1226 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1557 for (auto Reg : CLI.OutRegs) in fastLowerCall()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp839 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size(); in selectPatchpoint()
857 for (auto Reg : CLI.OutRegs) in selectPatchpoint()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2046 static void ComputeRegsForAlias(unsigned Reg, SmallSet<unsigned, 8> &OutRegs, in ComputeRegsForAlias() argument
2067 OutRegs.insert(Reg); in ComputeRegsForAlias()
2072 OutRegs.insert(OutReg); in ComputeRegsForAlias()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3046 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3251 for (auto Reg : CLI.OutRegs) in fastLowerCall()