Searched refs:OrDst (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMasking.cpp | 730 const MachineOperand &OrDst = PossibleOrSaveexec.getOperand(0); in tryRecordOrSaveexecXorSequence() local
732 if (OrDst.isReg() && OrSrc0.isReg()) { in tryRecordOrSaveexecXorSequence()
733 if ((XorSrc0.getReg() == Exec && XorSrc1.getReg() == OrDst.getReg()) || in tryRecordOrSaveexecXorSequence()
734 (XorSrc0.getReg() == OrDst.getReg() && XorSrc1.getReg() == Exec)) { in tryRecordOrSaveexecXorSequence()
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| H A D | SIPeepholeSDWA.cpp | 806 MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in matchSDWAOperand() local
807 assert(OrDst && OrDst->isReg()); in matchSDWAOperand()
810 OrDst, OrSDWADef, OrOtherDef, DstSel); in matchSDWAOperand()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2860 Register OrDst = MI.getOperand(0).getReg(); in matchRedundantOr() local
2861 LLT DstTy = MRI.getType(OrDst); in matchRedundantOr()
2878 if (canReplaceReg(OrDst, LHS, MRI) && in matchRedundantOr()
2885 if (canReplaceReg(OrDst, RHS, MRI) && in matchRedundantOr()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3246 Register OrDst = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select() local
3248 MIB.buildInstr(AArch64::ORRWrs, {OrDst}, {ZReg, SrcReg}).addImm(0); in select()
3249 SubregToRegSrc = OrDst; in select()
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