Searched refs:OpUndef (Results 1 – 12 of 12) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/instructions/ |
| H A D | nested-composites.ll | 17 ; CHECK-DAG: [[UNDEF_I16:%.+]] = OpUndef [[I16]] 18 ; CHECK-DAG: [[UNDEF_I64:%.+]] = OpUndef [[I64]] 19 ; CHECK-DAG: [[UNDEF_TY2:%.+]] = OpUndef [[TY2]]
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| H A D | call-complex-function.ll | 16 ; According to the Specification, the OpUndef can be defined in Function. 18 ; CHECK-DAG: [[UNDEF:%.+]] = OpUndef [[PAIR]]
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstrInfo.cpp | 42 case SPIRV::OpUndef: in isConstantInstr()
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| H A D | SPIRVInstrInfo.td | 91 def OpUndef: Op<1, (outs ID:$res), (ins TYPE:$type), "$res = OpUndef $type">;
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| H A D | SPIRVGlobalRegistry.cpp | 805 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) in getOrCreateUndef()
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| H A D | SPIRVInstructionSelector.cpp | 1047 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) in selectOpUndef()
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| /llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/ |
| H A D | AtomicCompareExchange.ll | 11 ; CHECK-SPIRV-DAG: %[[#UndefStruct:]] = OpUndef %[[#Struct]]
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| /llvm-project-15.0.7/mlir/lib/Target/SPIRV/Deserialization/ |
| H A D | DeserializeOps.cpp | 208 case spirv::Opcode::OpUndef: in processInstruction()
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/ |
| H A D | SPIRVCompositeOps.td | 315 operands, or using an OpUndef for one of the Vector operands.
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| H A D | SPIRVBase.td | 4008 def SPV_OC_OpUndef : I32EnumAttrCase<"OpUndef", 1>;
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| /llvm-project-15.0.7/mlir/lib/Target/SPIRV/Serialization/ |
| H A D | SerializeOps.cpp | 170 encodeInstructionInto(typesGlobalValues, spirv::Opcode::OpUndef, in processUndefOp()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 39081 APInt OpUndef, OpZero; in combineX86ShufflesRecursively() local 39084 if (getTargetShuffleInputs(Op, OpDemandedElts, OpInputs, OpMask, OpUndef, in combineX86ShufflesRecursively() 39101 OpZero = OpUndef = APInt::getNullValue(NumElts); in combineX86ShufflesRecursively() 39122 OpUndef = OpUndef.zext(NumSubVecs * OpMaskSize); in combineX86ShufflesRecursively() 39139 if (OpUndef[i] || OpZero[i] || isUndefOrZero(M)) in combineX86ShufflesRecursively() 39148 resolveTargetShuffleFromZeroables(OpMask, OpUndef, OpZero, in combineX86ShufflesRecursively() 39154 resolveTargetShuffleFromZeroables(OpMask, OpUndef, OpZero); in combineX86ShufflesRecursively() 39292 resolveTargetShuffleFromZeroables(ResolvedMask, OpUndef, OpZero); in combineX86ShufflesRecursively() 41529 APInt OpUndef, OpZero; in SimplifyDemandedVectorEltsForTargetNode() local 41532 if (!getTargetShuffleInputs(Op, DemandedElts, OpInputs, OpMask, OpUndef, in SimplifyDemandedVectorEltsForTargetNode() [all …]
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