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Searched refs:OpEntry (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp1589 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in selectDivRem() local
1601 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectDivRem()
1605 if (OpEntry.OpSignExtend) { in selectDivRem()
1606 if (OpEntry.IsOpSigned) in selectDivRem()
1608 TII.get(OpEntry.OpSignExtend)); in selectDivRem()
1635 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) in selectDivRem()
1647 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()
1669 .addReg(OpEntry.DivRemResultReg); in selectDivRem()
H A DX86FastISel.cpp1948 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local
1958 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()
1960 if (OpEntry.OpSignExtend) { in X86SelectDivRem()
1961 if (OpEntry.IsOpSigned) in X86SelectDivRem()
1963 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()
1989 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
2001 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()
2019 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()