Searched refs:OpBank (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 867 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop() local
868 if (OpBank != &AMDGPU::VGPRRegBank) { in executeInWaterfallLoop()
977 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI); in collectWaterfallOperands() local
978 if (OpBank->getID() != AMDGPU::SGPRRegBankID) in collectWaterfallOperands()
3592 auto OpBank = getRegBankID(MI.getOperand(I).getReg(), MRI); in getInstrMapping() local
3595 if (OpBank != AMDGPU::SGPRRegBankID) { in getInstrMapping()
3631 unsigned OpBank = Bank->getID(); in getInstrMapping() local
3632 ResultBank = regBankBoolUnion(ResultBank, OpBank); in getInstrMapping()
4801 auto OpBank = getRegBankID(Reg, MRI); in getInstrMapping() local
4803 OpdsMapping[I] = AMDGPU::getValueMapping(OpBank, Size); in getInstrMapping()
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| H A D | AMDGPUInstructionSelector.cpp | 2385 const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI); in getAddrModeInfo() local
2386 if (OpBank->getID() == AMDGPU::SGPRRegBankID) in getAddrModeInfo()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 731 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp() local
732 if (!OpBank) { in unsupportedBinOp()
737 if (PrevOpBank && OpBank != PrevOpBank) { in unsupportedBinOp()
741 PrevOpBank = OpBank; in unsupportedBinOp()
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