Searched refs:Op5 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 623 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
628 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
635 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
657 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
662 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
670 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6672 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm() local
6677 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
6680 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
6682 Op5.isImm() && !Op5.isImm0_508s4()); in tryConvertingToTwoOperandForm()
6703 const ARMOperand *LastOp = &Op5; in tryConvertingToTwoOperandForm()
6705 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && in tryConvertingToTwoOperandForm()
6731 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2154 const T4 &Op4, const T5 &Op5) {
2156 m_Argument<5>(Op5));
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1554 SDValue Op3, SDValue Op4, SDValue Op5);
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 9373 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
9374 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
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