| /llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 623 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
632 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL6RInstruction()
657 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
662 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
667 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL5RInstruction()
678 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstInstruction() local
683 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
686 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstInstruction()
697 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); in DecodeL4RSrcDstSrcDstInstruction() local
702 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); in DecodeL4RSrcDstSrcDstInstruction()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5576 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
5578 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
5580 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); in MatchAndEmitInstruction()
5597 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
5609 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
5619 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); in MatchAndEmitInstruction()
5640 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); in MatchAndEmitInstruction() local
5642 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
5661 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
5667 return Error(Op4.getStartLoc(), in MatchAndEmitInstruction()
[all …]
|
| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 2145 const T4 &Op4) {
2147 m_Argument<4>(Op4));
2154 const T4 &Op4, const T5 &Op5) {
2155 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3, Op4),
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1608 SDValue Op4 = Node->getOperand(4); in Select() local
1610 CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); in Select()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1552 SDValue Op3, SDValue Op4);
1554 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 433 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, vt4:$Op4)),
434 (inst $Op1, $Op2, $Op3, $Op4)>;
450 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
451 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
2287 …def : Pat<(nxv8f16 (op nxv8i1:$Op1, nxv8f16:$Op2, nxv8f16:$Op3, nxv8f16:$Op4, (i32 complexrotateop…
2288 (!cast<Instruction>(NAME # _H) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
2289 …def : Pat<(nxv4f32 (op nxv4i1:$Op1, nxv4f32:$Op2, nxv4f32:$Op3, nxv4f32:$Op4, (i32 complexrotateop…
2290 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
2291 …def : Pat<(nxv2f64 (op nxv2i1:$Op1, nxv2f64:$Op2, nxv2f64:$Op3, nxv2f64:$Op4, (i32 complexrotateop…
2292 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, $Op4, complexrotateop:$imm)>;
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 6168 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
6177 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
6186 OutOps.push_back(Op4); in SelectInlineAsmMemoryOperand()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6661 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm() local
6662 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6666 auto Op4Reg = Op4.getReg(); in tryConvertingToTwoOperandForm()
6710 LastOp = &Op4; in tryConvertingToTwoOperandForm()
6731 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 9366 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
9367 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
9373 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
9374 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| H A D | LegalizeIntegerTypes.cpp | 2182 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4)); in PromoteIntOp_PREFETCH() local
2184 Op2, Op3, Op4), in PromoteIntOp_PREFETCH()
|