Searched refs:Op1VT (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14697 EVT Op1VT = N->getOperand(1).getValueType(); in combineStoreFPToInt() local
14705 (Op1VT == MVT::i32 || Op1VT == MVT::i64 || in combineStoreFPToInt()
14706 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
14731 unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8; in combineStoreFPToInt()
14734 DAG.getValueType(Op1VT) }; in combineStoreFPToInt()
15157 EVT Op1VT = N->getOperand(1).getValueType(); in PerformDAGCombine() local
15176 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
15192 if (Op1VT.bitsGT(mVT)) { in PerformDAGCombine()
15197 if (Op1VT == MVT::i64) in PerformDAGCombine()
15231 if (Op1VT.isSimple()) { in PerformDAGCombine()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9003 EVT Op1VT = V1.getValueType(); in LowerCONCAT_VECTORS_i1() local
9005 assert(Op1VT == Op2VT && "Operand types don't match!"); in LowerCONCAT_VECTORS_i1()
9006 EVT VT = Op1VT.getDoubleNumVectorElementsVT(*DAG.getContext()); in LowerCONCAT_VECTORS_i1()
9008 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerCONCAT_VECTORS_i1()
9015 unsigned NumElts = 2 * Op1VT.getVectorNumElements(); in LowerCONCAT_VECTORS_i1()
9096 EVT Op1VT = V1.getValueType(); in LowerEXTRACT_SUBVECTOR() local
9105 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerEXTRACT_SUBVECTOR()
9534 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
9537 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
9539 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4407 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
4410 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
4412 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
|