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Searched refs:Off1 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp37 int64_t &Off0, int64_t &Off1) { in mayOverlapWrite() argument
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
54 const MachineInstr &MI = (Off0 < Off1) ? MI0 : MI1; in mayOverlapWrite()
58 return llabs(Off0 - Off1) < StoreSize; in mayOverlapWrite()
72 int64_t Off0, Off1; in tryCandidate() local
74 if (!mayOverlapWrite(*Instr0, *Instr1, Off0, Off1)) { in tryCandidate()
77 return Off0 < Off1; in tryCandidate()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonStoreWidening.cpp292 int Off1 = S1->getOperand(1).getImm(); in storesAreAdjacent() local
295 return (Off1 >= 0) ? Off1+S1MO.getSize() == unsigned(Off2) in storesAreAdjacent()
296 : int(Off1+S1MO.getSize()) == Off2; in storesAreAdjacent()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp271 SDValue Off1 = Load1->getOperand(OffIdx1); in areLoadsFromSameBasePtr() local
274 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1)) in areLoadsFromSameBasePtr()
278 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp7524 unsigned Off1 = rev ? 0 : NumElts / 2; in isVMOVNTruncMask() local
7528 if (M[i + 1] >= 0 && M[i + 1] != (int)(Off1 + i / 2)) in isVMOVNTruncMask()
16468 unsigned Off1 = Rev ? 0 : NumElts; in PerformSplittingToNarrowingStores() local
16473 if (M[I + 1] >= 0 && M[I + 1] != (int)(Off1 + I / 2)) in PerformSplittingToNarrowingStores()