Searched refs:OVF (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 730 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO() local
732 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
737 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 2971 SDValue OVF = Lo.getValue(1); in ExpandIntRes_ADDSUB() local
2975 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF); in ExpandIntRes_ADDSUB()
2978 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB()
2979 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
2982 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT); in ExpandIntRes_ADDSUB()
2983 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF); in ExpandIntRes_ADDSUB()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 161 // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc-
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