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Searched refs:OP3 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dfusion-elementwise-options.mlir61 // CHECK: %[[OP3:.+]] = linalg.generic {{.+}} ins(%[[ARG0]], %[[ARG1]], %[[OP1]], %[[OP2]]
62 // CHECK: return %[[OP3]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfp16-v4-instructions.ll160 ; CHECK-CVT-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
161 ; CHECK-CVT-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
194 ; CHECK-COMMON-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
195 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
196 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP3]].4s
241 ; CHECK-COMMON-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
242 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
243 ; CHECK-COMMON-NEXT: fcvtn v0.4h, [[OP3]].4s
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Defines.h34 OP3 = (1 << 5), enumerator
H A DR600InstrInfo.cpp123 (TargetFlags & R600_InstFlag::OP3)); in hasInstrModifiers()
1383 bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3; in getFlagOp()