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Searched refs:OP2 (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dassoc-cast-assoc.ll7 ; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 15
8 ; CHECK-NEXT: ret i5 [[OP2]]
19 ; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>
20 ; CHECK-NEXT: ret <2 x i32> [[OP2]]
31 ; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 11
32 ; CHECK-NEXT: ret i5 [[OP2]]
44 ; CHECK-NEXT: ret <2 x i32> [[OP2]]
57 ; CHECK-NEXT: [[OP2:%.*]] = zext i3 [[TMP1]] to i5
58 ; CHECK-NEXT: ret i5 [[OP2]]
69 ; CHECK-NEXT: [[OP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfp16-v4-instructions.ll8 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
9 ; CHECK-CVT-NEXT: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
33 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
49 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
65 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
159 ; CHECK-FP16-NEXT: scvtf v0.4h, [[OP2]]
173 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP2]]
195 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
208 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP2]]
220 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[OP2]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dfusion-elementwise-options.mlir60 // CHECK: %[[OP2:.+]] = linalg.generic {{.+}} ins(%[[ARG4]], %[[ARG5]]
61 // CHECK: %[[OP3:.+]] = linalg.generic {{.+}} ins(%[[ARG0]], %[[ARG1]], %[[OP1]], %[[OP2]]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dhwloop4.ll5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]],#-[[OP2:[0-9]+]]
6 ; CHECK-NOT: add([[OP0]],#[[OP2]])
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Defines.h39 OP2 = (1 << 11), enumerator
H A DR600InstrInfo.cpp122 (TargetFlags & R600_InstFlag::OP2) | in hasInstrModifiers()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp135 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp262 SDValue OP2 = LDAddrNode->getOperand(1); in PreprocessLoad() local
273 const ConstantSDNode *CDN = dyn_cast<ConstantSDNode>(OP2.getNode()); in PreprocessLoad()
/llvm-project-15.0.7/mlir/test/Conversion/PDLToPDLInterp/
H A Dpdl-to-pdl-interp-matcher.mlir430 // CHECK-DAG: %[[OP2:.*]] = pdl_interp.get_defining_op of %[[VAL2]]
432 // CHECK-DAG: pdl_interp.is_not_null %[[OP2]] : !pdl.operation
/llvm-project-15.0.7/flang/test/Fir/
H A Dconvert-to-llvm.fir1130 // CHECK: [[OP2:%.*]] = llvm.mlir.constant(24 : index) : i64
1133 // CHECK: [[TOTAL:%.*]] = llvm.mul [[MUL1]], [[OP2]] : i64
1149 // CHECK: [[OP2:%.*]] = llvm.mlir.constant(64 : index) : i64
1152 // CHECK: [[TOTAL:%.*]] = llvm.mul [[MUL1]], [[OP2]] : i64